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Nanoscale Vacuum Channel Transistors Operation in Poor Vacuum

Nanoscale vacuum channel transistors (NVCTs) using field emission sources could potentially have supe-rior performance compared to solid-state devices of similar channel length. This superior performance is due to ballistic transport of electrons, shorter transit time, and higher breakdown voltage in vacuum. Fur-thermore, there is no opportunity for ionization or avalanche carrier multiplication imbuing NVCTs with very high Johnson figure of merit (~1014 V/s). However, field emitters need ultra-high vacuum (UHV) for reli-able operation as the field emission process is sensitive to barrier height variations induced by adsorption/de-sorption of gas molecules. Small changes in the barrier height cause exponential variations in current. Poor vacuum also leads to the generation of energetic ions that bombard the emitters, altering their work func-tion and degrading electrical performance. Graphene can be used to nano-encapsulate the field emitter in UHV or a gas (e.g., He) with high ionization energy to overcome the UHV requirement. Separation of the electron tunneling region from the electron acceleration region enables emission of electrons in UHV and electron transport in poor vacuum, if not atmospheric conditions. For mechanical strength, a multi-layer graphene structure that is transparent to electrons while being impervious to gas molecules/ions is necessary. In this work, we studied the electron transparency and robustness of multi-layer graphene. We fabricated arrays of gated Si field emitters with 1-µm pitch and integrated a nanowire current limiter (Figure 1) that exhibits transistor-like characteristics. Using an energized multi-layer graphene/grid structure (Figure 2) in combination with emitter arrays, we achieved an electron transparency of ≈ 20%. We envision electron transparencies close to ~100% with an optimized design. Adopting this architecture for NVCTs will allow the realization of empty state electronics capable of functioning at higher frequencies (THz regime), higher power, and harsher conditions (high radiation and high temperature) than solid-state electronics.

Micro Rocket Engine using Steam Injector and Peroxide Decomposition

Rocket engines miniaturized and fabricated using silicon MEMS have been an active area of research for two decades. At these scales, miniaturized steam injectors like those used in Victorian-era steam locomotives are viable as a pumping mechanism and offer an alternative to pressure feed and high-speed turbo-pumps. Storing propellants at low pressure reduces tank mass, and this improves the vehicle empty-to-gross mass ratio; if one propellant is responsible for most of the propellant mass (e.g., oxidizer), injecting it while leaving the others solid or pressure-fed can still achieve much of the potential gain. Previously, the PI and his group demonstrated the feasibility of this pumping concept by designing and testing two ultraminiature-machined stainless steel micro jet injectors that pumped ethanol and by exploring liquid bi-propellant engine designs. Current efforts focus on designing a test article and fabrication process that integrates a jet injector, a decomposition chamber, and a thrust chamber with a solid or liquid fuel to form an injector-pumped partially-pressure-fed or hybrid micro rocket (see Figures 1 and 2). The proposed demonstration launch vehicle integrates these with suitably-sized propellant tanks and structures, derived from or like those found in hobby rocketry. Other applications have also been explored.

Ptychography Development for Soft X-ray Imaging at the Nanoscale

Ptychography, a powerful imaging modality, has been applied successfully to many experimental systems. Ptychography visualizes an extended object via re-trieval of the far-field phases of a wave scattered from it, from which a complex Fourier transform is extract-ed and a real space image formed by simple Fourier in-version. Removing the need for a high-quality imaging optic, ptychography improves the resolution of micros-copy experiments using high-energy probes, e.g., x-ray and electron microscopy, where lens quality limits ac-curacy. Ptychography also enables quantitative phase contrast imaging. X-ray ptychography in the Bragg geometry enables high-spatial-resolution quantitative studies of nanoscale structures in most electronic and magnetic materials: bulk crystals, thin films, hetero-interfaces, or composite devices. However, inevitable contamination by experimental sources of error limits progress in this area.X-ray ptychography requires high source coherence, monochromaticity, and stability plus precision motion of the source-forming optics. Studying electronic phases with soft x-rays in the Bragg geometry requires high vacuum, a stable cryogenic sample environment, and a full diffractometer; experiments inevitably face multiple serious sources of error. This challenge has deterred serious effort in this direction, despite enormous scientific potential. Intimate knowledge of these issues enabled us to develop computational tools to handle multiple qualitatively different sources of error simultaneously. We define experiment-specific forward models that incorporate parameters describing the dominant sources of error. Applying automatic differentiation and gradient descent-based optimization algorithms such as Adam allows reconstruction of contributions to the error during reconstruction of sample features.We validated our automatic differentiation-based approach with a series of proof-of-concept experiments at the CSX beamline of the National Synchrotron Light Source II (Brookhaven Natl Lab) in transmission and Bragg geometries. Experimental issues included extreme probe positioning errors, large fluctuations in the probe fluence, and reduced probe coherence. We successfully reconstructed test samples with known structures and produced consistent high-quality reconstructions from more realistic samples (see Figure 1). Future directions include studies of electronic symmetry breaking that are enabled by this novel capability, improvements to various error sources, and the ultimate resolution of the reconstructed images.

Control of the Density, Location, and Properties of Conducting Filaments in TiO2 by Chemical Disorder for Energy-efficient Neuromorphic Computing

Inspired by the efficiency of the brain, redox-based resistive switching (RS) random access memories are considered the next-generation devices to mimic neuromorphic core architectures for pattern recogni-tion and machine learning due to their predicted high memory density, energy efficiency, and speed. Within their metal−insulator−metal architecture, these de-vices store binary code information using the electric field-induced resistance change of the insulating layer by conductive filament (CF) formation and rupture. However, a lack of control on the location and spacing of CF formation, which occurs at chemical and struc-tural defects, and or their properties cause detrimental variation in the devices. We recently initiated a study on the effect of strain on the microstructure, chemistry, and RS properties of TiO2 thin films to get insights into defect formation in view of selectively doping along these defects to eliminate stochasticity in CF formation as schematically depicted in Figure 1.

Control of Conductive Filaments in Resistive Switching Oxides

There has been a growing interest in using specialized neuromorphic hardware for artificial neural network applications such as image and speech processing. These neuromorphic devices show promise for meet-ing the significant computational demands of such applications with higher speed and lower power con-sumption than software-based implementations. One approach to achieving this goal is through oxide thin film resistive switching devices arranged in a crossbar array configuration. Resistive switching can mimic sev-eral aspects of neural networks, such as short and long-term plasticity, via the dynamics of switching between multiple analog conductance states--dominated by the creation, annihilation, and movement of defects with-in the film (such as oxygen vacancies). These processes can be stochastic in nature and contribute significantly to device variability, both within and between individ-ual devices. This study focuses on reducing the variability of the set/reset voltages and enhancing control of the conductance state with voltage pulsing using model systems of HfO2 and SrTiO3 grown on Nb:SrTiO3 and Si/TiN substrates, by control of film synthesis parameters and composition. By comparing the electrical characteristics of a large number of devices (~100) from each processing condition, film growth conditions may be optimized for maximum resistive switching repeatability. Because the device requirements for practical resistive switching arrays are significant, controlling the variability of individual devices will likely be a consideration for every fabrication and processing step. This work provides a significant step towards understanding the mechanisms behind device variability and achieving devices that meet the strict requirements of neuromorphic computing.

Design and Characterization of Superconducting Nanowire-based Processors for Accelerating Deep Neural Network Training

Training of deep neural networks (DNNs) is a compu-tationally intensive task and requires massive volumes of data transfer. Performing these operations with the conventional von Neumann architectures creates un-manageable time and power costs. Recent studies have shown that mixed-signal designs involving crossbar architectures can achieve acceleration factors as high as 30,000× over the state-of-the-art digital processors. These approaches involve the use of non-volatile mem-ory elements as local processors. However, no technolo-gy has been developed to date that can satisfy the strict device requirements for the unit cell. This work presents the superconducting nanowire-based processing element as a cross-point device. The unit cell has many programmable non-volatile states that can be used to perform analog multiplication. Importantly, these states are intrinsically discrete due to the quantization of flux, which provides symmetric switching characteristics. The operation of these devices in a crossbar is described and verified with electro-thermal circuit simulations. Finally, validation of the concept in an actual DNN training task is shown using an emulator.

Metal Oxide Thin Films as the Basis of Memristive Nonvolatile Memory Devices

The design of silicon-based memory devices over the past 50+ years has driven the development of increas-ingly powerful and miniaturized computers with de-mand for increased computational power and data storage capacity continuing unabated. However, fun-damental physical limits are now complicating further downscaling. The oxide-based memristor, a simple M/I/M structure, in which the resistive state can be re-versibly switched by application of appropriate voltag-es, can replace classic transistors in the future. It has the potential to achieve operating power that is an or-der of magnitude lower than existing RAM technology and paves the way for neuromorphic memory devices relying on non-binary coding. Our studies focus on un-derstanding the mechanisms that lead to memristance in a variety of insulating and mixed ionic electronic conductors, thereby providing guidelines for material selection and for achieving improved device perfor-mance and robustness.

Ion-implantation and Multilayer Oxides with Conductive Spacers for Highly Consistent Resistive Switching Devices

Resistive switching devices are actively being pursued for use as the fundamental units in next-generation hardware deep-learning or neuromorphic systems. However, these devices are still tricky both to fabri-cate and to operate. Circuits that deploy these resistive switching devices in large arrays start off with a defi-cient capacity, operate erratically, and further degrade throughout their operational lifespan.We identified that simultaneous use of noble metal atom doping and of multilayer oxides will guarantee that devices have high yields after fabrication and high device-to-device and cycle-to-cycle switching consistency (Figure 1). Resistances in the low and high resistance states (LRS/HRS) span just 0.3 decades across devices and 0.05 decades across cycles on the logarithm scale, in comparison to a more typical span of 0.5 to 1.5 decades.Implanted Au atoms in Al2O3 act as bridging atoms for mobile oxygen vacancies in the formation and dissipation of conductive filaments of a hybrid composition. Density functional theory studies found that Au atoms stabilize neighboring oxygen vacancies, can act as a reservoir of vacancies, and enable the ease of switching between LRS and HRS. The DFT studies have also guided further experimental verifications that Pt and Pd are also highly suitable dopants to achieve high-consistency switching. Multi-bit switching could then be easily demonstrated without setting current compliances or using pulsing schemes.The strategy we used to achieve high yield and highly consistent resistive switching devices is broadly applicable to almost all material systems, which means that existing optimized devices can perhaps be further optimized without having to overhaul the existing material stack. The improvement in switching consistency will not just lead to more functional devices, but also simplify the study of future devices in uncovering more of the physics that governs the resistive switching mechanism.

Lithium Neuromorphic Computing and Memories

Advances over the last years on the understanding and implementation of memristor technology have posi-tioned memristors as a major candidate to overcome the current bottleneck in current electronic-based tran-sistors in terms of downscaling capabilities and energy consumption. In particular, current challenges pre-venting a widespread implementation of oxygen-based memristors in today’s integrated circuits include the need to address cycle-to-cycle and device-to-device variabilities while circumventing electroforming; these inherent issues are associated with the filamentary nature of the switching mechanism. An alternative strategy to tackle challenges might arise by looking at other mobile ions. It remains surprising that despite their fast diffusivity and stability, Li solid-state oxide conductors have been almost neglected as switching materials. On the other hand, the field of Li solid-state batteries has already shown that high Li conductivities are reachable and that the internal capacity to accu-mulate or deplete Li at oxide interfaces can vary over a huge range for electrode materials, enabling a perfect playground for performance-switching engineering.However, the defect chemistry leading to the switching behavior of Li-based materials and the impact of lithiation degree on their performance remain unclear. Our group is researching the problems for Li-based thin films. In particular, we report for the first time the non-volatile, non-filamentary bipolar resistive switching characteristics of lithium titanates compounds, Li4+3xTi5O12, as a function of the lithiation degree. We have employed a recently proposed strategy to overcome Li loss during thin film deposition and finely control the final lithiation degree of the films to create delithiated Li4Ti5O12 and overlithiated Li7Ti5O12 memristive devices. Changing the Li content from a delithiated to an overlithiated phase results in the capability to tune the performance in a wide range in terms of accessible resistance window (from ratios of 102 to 106 at low voltage operation), symmetry (from highly asymmetric to symmetric behavior, respectively) and retention (from a few minutes up to 105 s at room temperature, respectively), among others. In other words, controlling the lithiation degree might offer a suitable path to reduce the stochasticity from which current filamentary memristive devices inherently suffer, mainly due to the difficulties in controlling the number of vacancies generated, and paves the way to further control of ionic migration for novel nanoelectronic devices.

Sub-5-nm Fin-width InGaAs FinFETs by Thermal Atomic Layer Etching

As complementary metal-oxide semiconductor (CMOS) technology continues to scale down and transistor structures become more three-dimensional, semicon-ductor manufacturing is increasingly more challeng-ing. In recent years, 3D transistors with sub-10-nm physical dimensions have been demonstrated. Pushing forward requires breakthroughs in device fabrication technologies with sub-nm-scale precision and fidelity. In this research, we demonstrated the first III-V 3D transistors with sub-5-nm fin width. This size is made possible by the development of a novel fabrication technology called thermal atomic layer etching (ALE). Thermal ALE can be thought of as the reverse of atomic layer deposition (ALD). Thermal ALE is a plasma-free and benign chemical process that can be integrated with ALD in an in-situ approach in the same reactor. In this work, we have demonstrated the first thermal ALE on III-V compound semiconductors. We achieved a highly controllable etching rate of InGaAs of merely 0.2 Å/cycle. Figure 1 shows a fully suspended InGaAs fin with minimum fin width of 3 nm, covered by an Al2O3/W gate stack, fabricated by the in-situ thermal ALE-ALD technique. Moreover, we illustrated the device worthiness of the thermal ALE technique by fabricating the most aggressively scaled InGaAs fin field-effect transistors (FinFETs) to date, with record fin width down to 2.5 nm. We demonstrated working FinFETs with 2.5-nm fin width and 60-nm gate length, as shown in the subthreshold characteristics in Figure 2. Record ON- and OFF-state transistor characteristics highlight the extraordinary device potential of the in-situ ALE-ALD process.

Impact of Fin Width on Performance in Nanometer-scale InGaAs FinFETs

InGaAs is a promising n-channel material candidate for future CMOS technology due to its superior electron transport properties and low-voltage operation. In-GaAs fin field-effect transistors (FinFETs) have drawn much interest as they provide both superb transport advantages and great scaling potential. Recently, our group has demonstrated impressive InGaAs FinFETs with fin width down to 5 nm and record channel-aspect ratio. Figure 1 shows cross-sectional schematics of a device across the fin and along the channel directions. The channel is 50-nm-thick InGaAs, and the gate oxide consists of 1 monolayer of Al2O3 and 3-nm HfO2 deposited by atomic layer deposition. These are some of the most aggressively scaled and highest-performing InGaAs FinFETs in the world. Our results show a rapid degradation in performance as the fin width scales down to single-nanometer dimensions. Figure 2 shows that as fin width narrows below about 10 nm, the DC peak transconductance (gm,max) sharply decreases. Our study focuses on understanding the underlying reason behind such degradation.One of the most critical challenges facing III-V semiconductors is the lack of a good native oxide. Severe electron trapping in the oxide has been reported, resulting in hysteresis, threshold voltage instability, and frequency dispersion in InGaAs metal-oxide semiconductor FETs (MOSFETs). In this work, the same problematic issues are observed in our FinFETs. To gain deeper understanding, we use high-frequency measurement techniques to isolate the intrinsic characteristics in InGaAs FinFETs free from the influence of oxide trapping. We find that at 1 GHz, where most oxide traps are unresponsive, gm,max extracted from S-parameters is much higher than DC and degrades more slowly (Figure 2). This suggests significantly higher intrinsic performance potential even in narrow InGaAs FinFETs than what is observed under DC conditions. Our results also highlight the importance of minimizing oxide trapping in future scaled InGaAs FinFETs.

Excess Off-state Current in InGaAs FinFETs

InGaAs is a promising channel material candidate for CMOS technologies beyond the 7-nm node. In these di-mensions, only high-aspect-ratio 3D transistors with a fin or nanowire configuration can deliver the necessary performance while suppressing short-channel effects. Recently, impressive InGaAs FinFET (Figure 1) proto-types have been demonstrated.However, InGaAs FinFETs are challenged by relatively high leakage of current in the OFF state (Figure 2). This leakage originates from band-to-band tunneling at the drain end of the channel that is amplified by a parasitic bipolar effect as a result of its floating body. In this work, we present a simple model of the parasitic bipolar effect in InGaAs FinFETs that captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain of the parasitic bipolar junction transistor. The model enables the extraction of the carrier diffusion length, which exhibits the predicted dependence on fin width. For short gate length transistors, source recombination is shown to dominate, and the parasitic bipolar gain scales with the inverse of the gate length.

Digital-etch Effect on Transport Properties of III-V Fins

One of the key process technologies to improve the interface quality of modern III-V transistors is digital etching (DE). DE is a self-limiting etching process that consists of dry oxidation of the semiconductor surface and wet etching of the oxide. DE is also the last process step before the gate oxide is deposited over the fins in FinFETs . DE, therefore, plays a crucial role in surface preparation and holds the key to further improve-ments to device transport and electrostatics.In this work, we compare the electrical performance of two sets of InGaAs FinFETs (Figure 1a) processed side by side that differ only in the type of DE that is applied. In one case, the oxide removal step was accomplished using H2SO4; in the other, HCl was used. While the etching property is similar for both processes, the surface termination is different (Figure 1b). Consequently, each treatment results in a different interface trap density (Dit) profile. To study the impact of surface treatments, we compare the electrical performance of the devices, as summarized in Figure 2. There are a few notable differences. In the OFF state, the HCl sample shows a larger subthreshold swing than the H2SO4 sample (Figure 2a). This suggests that HCl treatment results in a higher interface state density (Dit) toward the valence band. In the ON state, however, the intrinsic transconductance, gm,i, exhibits a peculiar trend. For wide fins, the HCl sample shows higher performance, but in very narrow fins (Wf<20 nm), H2SO4 performs better (Figure 2b). This implies that HCl yields higher mobility but lower carrier concentration at comparable overdrive. For aggressively scaled fins, the carrier concentration in the fin becomes comparable to Dit, and, as a result, the intrinsic gm of H2SO4 sample prevails.

InGaAs MOSFET with Integrated Hf0.5Zr0.5O2 in the Gate Stack for Investigating the Dynamic Operation of Negative Capacitance

Achieving negative capacitance (NC) by incorporating a ferroelectric (FE) material in the gate stack of a met-al-oxide semiconductor field-effect transistor (MOS-FET) has recently attracted considerable interest. This interest is because of its potential for achieving a steep subthreshold swing in ultra-scaled semiconductor de-vices. Among the FE materials, HfxZr1-xO (HZO) thin film is the most promising and readily available option, because it is scalable and fully compatible with the current complementary metal-oxide semiconductor process. For these reasons, various experiments and simulations have been demonstrated so far. However, the dynamic response of the NC effect remains con-tentious and unclear. In this work, we present InGaAs MOSFETs with integrated Hf0.5Zr0.5O2 as a first step in the investigation of the dynamic operation of NCFETs. Figure 1 shows the schematic of a typical self-aligned device fabricated through a gate-last process. The gate stack was formed with 4 nm of Al2O3 as an interlayer and 10 nm of HZO, followed by a TiN layer deposited by an in-situ atomic layer deposition process. Rapid thermal anneal is performed at 500 °C for 1 min to activate the FE property of the HZO film, as confirmed by the hysteresis loop in Figure 2a. The control device has an identical structure except for the absence of the HZO layer in the gate stack. Integrating the HZO into the gate stack shows a plausible FE characteristic, which is ΔVth<0 during a full cycle sweep of the subthreshold characteristics, as shown in Figure 2b. However, the devices do not manifest the NC effect, for example, sub-60-mV/decade subthreshold swing and ON-current boost, even though the capacitance matching process was performed. In conclusion, we have observed characteristics consistent with the FE effect in InGaAs MOSFETs that incorporate HZO in the gate stack. Furthermore, we realize the device should be fabricated with a thinner interlayer to scrutinize the NC effect in the high-frequency regime.

High-temperature Electronics Based on GaN Technology

Compared to conventional Si or GaAs based devices, wide-bandgap GaN has fundamental advantages for high-temperature applications thanks to its very low thermal carrier generation below 1000 °C. However, in spite of the excellent performance shown by early high-temperature prototypes, several issues in traditional lateral AlGaN/GaN high-electron mobility transistors (HEMTs) could cause early degradation and failure under high-temperature operation (over 300 °C). These include ohmic degradation, gate leakage, buffer leakage, and poor passivation. To enable digital circuit processing, it is critical to have enhancement-mode HEMTs, while two-dimensional electron gas induced by AlGaN/GaN heterostructure makes HEMTs into natural depletion-mode devices. Gate injection transistors (GIT) are being considered to overcome this problem at high temperatures.Our previously reported tungsten Si-implanted ohmic contact shows great thermal stability over 300 °C by combining a refractory metal such as tungsten (W) with Si-ion implantation, which locally dopes the material n-type and reduces the contact resistance. However, ion implantation technology in GaN is still challenging due to activation and damage recovery. The implanted contact performance is limited by high access resistance. High-temperature activation annealing over 1200 °C would cause irreversible lattice relaxation and degrade the AlGaN/GaN heterostructure quality, as shown in Figure 1. The implanted contact performance at different activation annealing condition is also shown in Figure 2.

Novel GaN Transistor Design for High Linearity Applications

Enhancing the linearity of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) is essen-tial for future radio frequency (RF) applications that require extremely low intermodulation distortion and gain compression. Existing power amplifiers with high linearity specifications make use of gallium arse-nide (GaAs)-based heterostructure bipolar transistors (HBTs) or digital pre-distortion, but these solutions are insufficient to fulfill the needs of next-generation power amplifiers operating at the Ka band and beyond. Therefore, device-level solutions are required to im-prove the linearity of power amplifiers. This study fo-cuses on the origins of device non-linearities in GaN-based transconductance amplifiers (Classes A through C) and proposes device-level solutions to enhance the linearity at the amplifier level.First, the drop in transconductance (gm) at high current levels observed in GaN transistors can be miti-gated with either self-aligned or fin field-effect transis-tor- (FinFET-) like structures. This is due to the higher current-driving capability of the source access region on these devices.Second, the large second derivative of the transcon-ductance with respect to gate-source voltage (Vgs) (gm" or gm3) results in gain compression in the RF amplifier. This can be overcome by using a new generation of en-gineered FinFET transistors where the width of each fin is optimized for minimizing gm".Third, the non-linear behavior of the device capac-itances (Cgs, Cgd) with gate bias voltage plays a signifi-cant role in limiting the maximum achievable linearity of the amplifier, especially at large signal swings. Nano-structures could be used to improve the capacitance behavior and hence linearity.Last, but not least, memory effects due to surface traps and buffer traps/defects contribute to non-linear-ity in amplifiers. They, too, could be overcome through the use of nanostructures.

Vertical GaN Fin Transistors for RF Applications

The demand for improved wireless connectivity and data speeds has continuously increased and outpaces hardware’s abilities. Transistors for radio frequency (RF) amplifiers must be developed to satisfy this grow-ing market. Recently, lateral GaN-based high electron mobility transistors (HEMTs) have succeeded in the RF power market. However, the strong confinement of current near the surface plagues HEMTs with current collapse and self-heating. To circumvent these limita-tions, we use a vertical transistor design where current conducts through the bulk of the material, minimizing surface effects. This vertical design offers reduced cur-rent collapse, area independent breakdown, increased power density, and improved heat dissipation, which enable unmatched RF performance. Figure 1 shows a schematic of our vertical transistors. A fin-based structure adopted from devices we developed for vertical GaN power transistors confines current. Us-ing fins has the added benefit of improving linearity through threshold voltage engineering, where varying the width of each fin optimizes the transconductance curve. With 100-nm gate lengths and optimized drift re-gions, these devices are designed for 30 GHz operation with 200 V breakdown.Figure 2 shows the first GaN RF fin transistors fabricated at MTL. To fabricate them, an array of 200-nm fins is patterned with electron beam lithography and etched using a combined dry and wet etching technique that produces highly vertical, smooth sidewalls. Forming the gate uses a sputter and etch-back process to allow gate lengths unconstrained by lithographic resolution limits. A conformal silicon dioxide coating fills spaces between fins and is subsequently etched back to expose the tops of the fins. Ohmic metal for the source and drain is finally deposited. Keeping all contacts on the top surface and utilizing an insulating, high thermal conductivity substrate like silicon carbide enables integration with existing microwave integrated circuits to meet the demands of the next generation of wireless communication systems.

GaN Power Transistor Reliability

Gallium nitride (GaN) metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) tech-nology is the most recent development in the power semiconductor market. Owing to its large bandgap and other unique material properties, GaN exhibits a breakdown field up to ten-fold higher than Si. The MIS field-effect transistor (FET) architecture was adopted to optimize the breakdown voltage and demonstrate reliable and highly-efficient operation at and over 650 V. Combined with low on-resistance and fast switching capability, the GaN MISFET is a promising platform for numerous applications in the power electronics mar-ket.A successful commercial technology must meet strict reliability requirements. We are interested in gate oxide breakdown through a process known as time-dependent dielectric breakdown (TDDB) in the OFF state of transistor operation. This occurs with a large drain-source voltage and the channel turned off. For estimation of transistor lifetime under operating conditions in an effective manner, suitable acceleration of the degradation rate needs to be introduced. This is often done through voltage or temperature acceleration. However, since the GaN MISFET architecture employs a conductive substrate, a concern arises about substrate leakage that, under accelerated conditions, can trigger a potential vertical breakdown path through the buffer layer. Our work seeks to develop a test procedure for isolating and evaluating transistor time-to-failure due to TDDB by suitable temperature and voltage acceleration and to distinguish this from other failure mechanisms.Commercial prototype devices are tested at the Microsystems Technology Laboratories with only one acceleration factor changed at a time. The experimental design accounts for higher stress voltages or temperatures at which devices break in minutes. Weibull distributions are then fitted to the data as a function of different conditions; from these results, the acceleration factors and lifetime estimations are derived. This method is effective at giving intrinsic failure modes a physical interpretation and at predicting mean-time-to-failure under use conditions. Figure 1 shows gate current for five devices measured under the same stress condition. Figure 2 shows the Weibull distribution plot for these devices with a line fit and a shape parameter β estimate of 2.8.

Time-dependent Dielectric Breakdown under AC Stress in GaN MIS-HEMTs

GaN has emerged as a promising next-generation can-didate for high-performance energy-efficient electron-ics. In particular, the GaN metal-insulator-semicon-ductor high-electron-mobility transistor (MIS-HEMT) has been identified recently as a promising candidate for high-voltage and high-power applications due to its high current drive while minimizing gate leakage. However, reliability concerns with this device type are hampering its widespread commercial deployment. A key reliability issue is time-dependent dielectric break-down (TDDB), in which prolonged electrical stress leads to catastrophic breakdown of the gate dielectric. There has recently been great progress in understand-ing TDDB in GaN FETs. However, much of the work to date has been done under constant voltage stress con-ditions, mostly due to ease of instrumentation. Here, we investigate time-dependent dielectric breakdown (TDDB) in AlGaN/GaN MIS-HEMTs under forward bias AC stress, which better emulates real-world operational conditions. To this end, we have performed TDDB experiments across a wide range of frequencies, temperatures, and recovery voltage levels. We find that TDDB under AC stress shows longer breakdown times than under DC stress and that this increase is more prominent with higher frequency, lower-temperature, and more negative recovery voltage. We hypothesize that this is due to the dynamics of the gate stack in GaN MIS-HEMTs biased with a high positive gate voltage. Under these conditions, a second electron channel forms at the dielectric/AlGaN interface. This process is relatively slow as these electrons come from the 2DEG at the AlGaN/GaN interface and must overcome the energy barrier presented by the AlGaN. At the same gate voltage, then, the electric field across the gate oxide is lower in magnitude under AC stress at high enough frequency than under DC stress, explaining the obtained results.

Reliability of GaN High-electron-mobility Transistors

Gallium nitride-based high-electron-mobility tran-sistors (GaN HEMTs) are particularly attractive for high-power and high-frequency applications. While there have been some successful commercialization of these devices, large-scale market adoption has not yet occurred. This lack is partially due to an unclear under-standing of the origin of low device fabrication yield and reliability.Using research devices made by collaborators, we have systematically studied the origin of high gate-leakage currents in AlGaN/GaN HEMTs. Devices that initially had a low gate-leakage current (good devices) were compared with ones that had a high gate-leakage current (bad devices). The apparent zero-bias Schottky barrier height of bad devices (0.4 < ϕB0 < 0.62 eV) was found to be lower than that of the good devices (ϕB0=0.79 eV). From transmission electron microscopy and electron energy loss spectroscopy analysis, we found that this difference is due to the presence of carbon impurities in the nickel layer in the gate region, as shown in Figure 1. The carbon is likely the residue from a lift-off process.In ongoing research, we are also characterizing the reliability of commercial GaN HEMTs. Different failure modes have been identified for both on-state and off-state testing, as shown in Figure 2. Statistical reliability models will be developed and compared with research devices.

MIT Virtual Source Ferroelectric FET (MVSFE) Model: Application to Scaled-Lg FeFET Analog Synapses

Conventional multi-purpose hardware based on von-Neumann architecture does not satisfy the energy-efficiency requirements of large-scale implementations of deep neural networks (DNN). Hardware accelerators are, therefore, key to improve the power efficiency of many big data applications based on deep learning, such as image classification and speech recognition. Emerging non-volatile memory devices such as resistive random-access memory, phase change memory, floating gate memory, and ferroelectric field-effect transistors (FeFETs) are potential candidates for these DNN accelerators due to their synaptic functionality, i.e., analog conductance modulation. FeFET analog synapses are 3-terminal devices and one of the most promising non-volatile memory devices that can improve the classification accuracy and yield low latency in neuromorphic accelerators. This is due to their high conductance ratio, operation capability with sub-100-ns pulse, and seamless integration with CMOS process flow. The initial proof-of-concept FeFET synapses have been demonstrated in a custom-built Si platform with large device footprint (Lg = 0.6 µm, W=20 µm). This work presents a comprehensive physics-based compact modeling platform, MIT Virtual Source Ferroelectric FET (MVSFET), that is used to study the scaled (Lg =45 nm) three-terminal FeFETs calibrated against a state-of-the-art highly scaled MOSFET. The MVSFE model captures FeFET characteristics by combining the MVS-model that describes underlying Si-MOSFET ballistic transport together with Preisach (static) and VDST (dynamic) models that govern the full-dynamics of Fe-oxide. The robustness of the model verified for synaptic operation with different pulse schemes was used to predict the advantage of technology scaling in reduced latency and improved energy efficiency while maintaining a high classification accuracy in a system-level multilayer perceptron network. The current work reveals the potential of FeFET analog synapses for system-level applications used in advanced technological node platforms.

X3D: Heterogeneous Monolithic 3D Integration of “X” (Arbitrary) Nanowires: Silicon, III-V, and Carbon Nanotubes

We experimentally demonstrate a new paradigm for monolithic three-dimensional (3D) integration: X3D, which enables a wide range of semiconductors includ-ing silicon (Si), III-V, and nanotechnologies such as car-bon nanotubes (CNTs) to be heterogeneously integrat-ed together in monolithic 3D integrated systems (Fig. 1). Such flexible heterogeneous integration has the po-tential for a wide range of applications, as each layer of monolithic X3D integrated circuits (ICs) can be custom-ized for specific functionality (e.g., wide-bandgap III-V-based circuits for power management, CNT field-effect transistors (CNFETs) for energy-efficient computing, and tailored materials for custom sensors or imagers). As a case study, we experimentally demonstrate monolithic X3D ICs with 5 vertical circuit layers heterogeneously integrating 3 different semiconductors: Si junctionless nanowire field-effect transistors (JNFETs), III-V JNFETs, and CNFETs (also junctionless). The layers of monolithic X3D IC are, from bottom to top: Si p-JNFETs, n-CNFETs, Si n-JNFETs, p-CNFETs, and III-V n-JNFETs (Fig. 2). Each layer is fabricated using an identical process flow for ease of integration. Importantly, we show that circuits fabricated on each vertical layer are agnostic to subsequent monolithic X3D processing, experimentally demonstrating the ability to interleave these “X” (arbitrary) semiconductors in arbitrary vertical ordering (Fig. 3). As a final demonstration, we fabricate complementary digital logic circuits comprising different technologies that span multiple vertical circuit layers. This work demonstrates a new paradigm for ICs, allowing for flexible and customizable electronic systems.

Strong Coupling between Cavity Photons and Nano-magnet Magnons

Coupled microwave photon-magnon hybrid systems offer promising applications by harnessing various magnon physics. At present, to realize high coupling strength between the two subsystems, bulky ferro-magnets with large spin numbers N are utilized, which limits their potential applications for scalable quantum information processing. By enhancing single-spin cou-pling strength using lithographically defined super-conducting resonators, we report high cooperativities between a resonator mode and a Kittel mode in nano-meter-thick Permalloy wires. The on-chip, lithographically scalable, and super-conducting quantum-circuit-compatible design provides a direct route toward realizing hybrid quantum systems with nanomagnets, whose coupling strength can be precisely engineered and whose various mechanisms derived from spintronic studies can control dynamic properties. We pattern superconducting niobium films into coplanar waveguide (CPW) resonators and deposit nanometer-thick Py wires on top of them. An in-plane magnetic field is applied to adjust the resonance frequency of the Kittel mode in Py, which interacts with the resonator mode to create mode-splitting near resonance. By fitting the resonance mode’s evolution, we confirmed the scaling of g with N by varying the Py sizes. To further lower N, we employ low-impedance resonators that greatly enhance the magnetic field near the Py wires. A g/2π of 74.5 MHz is obtained for 40um × 2um × 10nm Py, corresponding to 4x1010 spins. Compared with previous works, our experiment shows a more than six orders-of-magnitude reduction in spin number. This highly engineerable device design and the large coupling strength with nanomagnets provide a direct avenue towards scalable hybrid quantum systems that can benefit from various magnon physics, including nonlinearity, synchronized coupling, non-Hermitian physics, and current- or voltage-controlled magnetic dynamics.

Magnon Spin Generation and Transport in Heavy Metal-magnetic Insulator-ferromagnet Hybrid Structure

Magnons (or spin waves) are collective excitations of electrons’ spin angular momenta in magnetic or non-magnetic materials. Magnons can be used to trans-port spin current and enable information transmission with much higher energy efficiency than conducting electron spin current. The excitation and tunabili-ty of magnons in low-damping magnetic materials are particularly interesting because they could offer much longer magnon propagation length and poten-tial broad spintronic applications. However, the exci-tation of magnons in ferromagnetic metals is usually accompanied by a rectification effect that can hinder the effective detection of magnon spin current. The goal of our project is to utilize a heavy metal/magnetic insulator/ferromagnet hybrid structure for definitive and efficient magnon spin generation, transport, and manipulation. In our work, a platinum (Pt)/yttrium iron garnet (YIG)/permalloy (Py) hybrid structure is studied, as depicted in Figure 1(a), where YIG is a low-damping magnetic insulator, Py is a low-damping ferromagnetic metal, and the whole structure is grown on the gadolinium gallium garnet (GGG) substrate by magnetron sputtering. Through external microwave excitation, the YIG layer and the Py layer can be excited to reach the ferromagnetic resonance (FMR) modes individually, as shown in Figure 1(b). Spin current generated by the Py spin pumping process can transmit through the YIG layer and be converted to voltage signal in the platinum (Pt) layer through the inverse spin Hall effect, where the rectification effect from the Py layer can be completely ruled out. More importantly, the perpendicular standing spin waves (PSSWs) have been detected in the YIG layer, as shown in Figure 1(b). At specific frequency (~7 GHz), the PSSWs in YIG can be coupled with the magnon mode in Py, as indicated in Figure 1(c), and facilitate the magnon spin transport from the Py layer to the bottom Pt layer, as demonstrated by Figure 1(d). This result indicates that the PSSWs in the YIG layer could offer additional tunability to control the magnon spin transmission from Py to the bottom Pt layer, which is promising for building magnon spin switches or amplifiers for magnonic device applications.

Tunable Spin-charge Conversion across the Metal-insulator Transition in Vanadium Dioxide

The charge-to-spin conversion efficiency is a crucial parameter in determining the performance of many useful spintronic materials. Usually, this conversion efficiency is an intrinsic material property, which can-not be easily modified without invoking chemical or structural changes in the underlying system. Here we demonstrate successful tuning of charge-spin conver-sion efficiency via the metal-insulator transition in a prototypical metal-insulator transition material. Vanadium dioxide (VO2), a quintessential strongly correlated electron compound, undergoes a temperature-driven structural phase transition near room temperature. This abrupt change in its electrical, optical, thermal, and magnetic properties at transition has generated great interest from both technological and fundamental research perspectives. By employing ferromagnetic-reso- nance-driven spin pumping and the inverse spin Hall effect measurement, we find that the pumped spin signal and charge-spin conversion efficiency undergo a swift, dramatic enhancement upon transition. The large enhancement (80%) in the spin pumping signal across the metal-insulator transition provides the first evidence of variable spin-charge conversions of this material. In combination with the recently observed electric-field, irradiation, or strain mediated phase transitions in VO2, this tunable spin-charge conversion can be used to make practical spintronic devices. The abrupt, dramatic change in the structural and electrical properties of this material, therefore, provides additional knobs to modulate the spin-charge conversion efficiency, leading to extra flexibilities in spintronic device design as well as providing new functionalities for spintronic devices, such as tunable spin-based memory and energy-harvesting devices.

Mutual Control of Coherent Spin Waves and Magnetic Domain Walls in a Magnonic Device

Spin waves, the collective excitation of electronic spins inside magnetic materials, offer new opportunities for wave-based computing. Here we experimental-ly demonstrate interactions between spin waves and magnetic domain walls, where the magnetic domain walls manipulate the phase and magnitude of spin waves and a strong spin wave, in turn, moves the posi-tion of magnetic domain walls. The discovery of mutu-al control between a spin wave and a magnetic domain wall can lead to efficient mechanisms for modulating spin wave propagation, which opens the possibility of realizing all-magnon-based reading/writing devices. In the first part of this work, we experimentally demonstrate that nanometer-wide magnetic domain walls can be used to manipulate the phase and magnitude of coherent spin waves in a non-volatile manner. A coherent spin wave is excited and detected in Co/Ni multilayers, the perpendicular magnetic anisotropy, and a relatively low damping factor, which allows the coexistence of domain walls and zero-field coherent spin wave excitation. By comparing the transmitted signals of the spin wave in a device with and without a domain wall, we observe a more than 10-dB change in magnitude and a nearly 180° shift in phase when the spin wave passes through the domain wall. In the second part of this work, we observe that the domain wall moves opposite the direction of the spin wave propagation and reaches maximum efficiency at the spin wave resonance frequency, which is consistent with the picture of spin transfer torque from the magnon spin current. The combination of these two effects can potentially provide a platform for realizing efficient spin-wave-based memory, computing, and information processing that lie in the domain of single spin waves.

Research on CMOS-compatible High-k Dielectrics for Magneto-ionic Memory

High-k dielectrics play a key role in modern microelec-tronic circuitry, given their ability to provide reduced leakage currents while providing adequate capacitance in ever-smaller nano-dimensioned metal-oxide semi-conductor field-effect transistor (MOSFET) devices. Re-cently, the Beach group at MIT demonstrated the abil-ity to modulate the magnetic properties of transition metal thin films by electrical bias across thin films of Gd2O31. The reversible switching was demonstrated to be assisted by the electro-migration of ions to and away from the transition metal/Gd2O3 interface. This novel process, now called “magneto-ionic control,” creates new opportunities for nonvolatile information storage. To better understand the mechanisms of ionic transport in these devices, we are examining the defect, electrical, and transport properties of Gd2O3 via impedance spectra as a function of temperature and oxygen partial pressure considering Gd2O3 as a model oxide for ionic migration-controlled devices. In this research, we find that Gd2O3 can be an electronic or mixed ionic-electronic conductor at high-temperature depending on dopant type, concentration, and phase. This research is being extended to the lower-temperature regime to understand the correlations between the behavior of such devices and their defect chemistry.

Sub-10 nm Diameter InGaAs Vertical Nanowire MOSFETs

In future logic technology for the Internet of Things and mobile applications, reducing transistor power consump-tion is of paramount importance. Transistor technolo-gies based on III-V materials are widely considered as a leading solution to lower power dissipation by enabling dramatic reductions in the transistor supply voltage. Ver-tical nanowire (VNW) transistor technology holds prom-ise as the ultimately scalable device architecture.In this work, we present the smallest vertical nanowire transistors of any kind in any semiconductor system. These devices are sub-10 nm diameter InGaAs VNW metal–oxide–semiconductor field-effect transistors (MOSFETs). They are fabricated by a top-down approach, using reactive ion etching, alcohol-based digital etch, and Ni alloyed contacts. A record ON current of 350 μA/μm at OFF current of 100 nA/μm and supply voltage of 0.5 V is obtained in a 7 nm diameter device. The same device exhibits a peak transconductance of 1.7 mS/μm and minimal subthreshold swing of 90 mV/dec at a drain voltage of 0.5 V. This yields the highest quality factor (defined as the ratio between transconductance and subthreshold swing) of 19 reported in vertical nanowire transistors. Excellent scaling behavior is observed with peak transconductance and ON current increasing as the diameter is shrunk down to 7 nm. The performance of our devices exceeds that of the best Si/Ge transistor by a factor of two at half the supply voltage.

10-nm Fin-Width InGaSb p-Channel FinFETs

Recently, III-V multi-gate MOSFETs have attracted great interest to replace silicon in future CMOS tech-nology. This is due to III-V semiconductor’s outstand-ing carrier transport properties. Although impressive n-type transistors have been demonstrated on materi-als such as InAs and InGaAs, research in III-V p-chan-nel devices is lagging. The antimonide system, such as InGaSb, has the highest hole mobility among all III-V compound semiconductors, and its hole mobility can be further improved by applying compressive strain. Therefore, InGaSb is regarded as one of the most prom-ising semiconductors to replace p channel Si MOSFETs.FinFET is a nonplanar transistor in which the conducting channel sticks out of the wafer top in a similar way as the fin of a shark above the ocean surface. In a FinFET, the gate wraps around the fin helping to reduce leakage current when the device is OFF and mitigating short-channel effects. FinFET is the state of the art transistor architecture in current Si CMOS technology, and demonstration of III-V FinFETs is imperative.In this work, we greatly advance the state-of-the-art of antimonide-based electronics by demonstrating deeply-scaled InGaSb p-channel FinFETs through a fully CMOS-compatible fabrication process. To achieve this, we have developed a novel antimonide-compatible digital etch technology, which has a consistent etch rate of 2 nm/cycle on InGaSb. It is the first demonstration of digital etch on InGaSb-based transistors of any kind. The new technologies enabled the first fabricated InGaSb FinFETs featuring fin widths down to 10 nm and gate lengths of 20 nm. Single fin transistors with fin width of 10 nm and channel height of 23 nm (aspect ratio of 2.3) have achieved a record transconductance of 160 μS/μm at VDS = 0.5 V. When normalized to device footprint, we achieve a record transconductance of 704 μS/μm. Digital etch has been shown to effectively improve the turn-off characteristics of the devices. This work not only highlights the potential of InGaSb p-channel multigate MOSFETs, but also pushes the state-of-the-art of antimonide fabrication technology significantly for general applications in which the antimonide-based compounds can shine.

Digital-etch Effect on Transport Properties of III-V Fins

InGaAs is a promising candidate as channel material for CMOS technologies beyond the 7 nm node. In this dimensional range, only high aspect-ratio (AR) 3-D tran-sistors with a fin or nanowire configuration can deliver the necessary performance. Impressive InGaAs FinFET prototypes have been demonstrated recently. However, as the fin width is scaled down to 10 nm, severe ON-cur-rent degradation is observed. The origin of this perfor-mance degradation is largely related to the quality of the high-K/semiconductor interface at the fin sidewalls. One of the key process technologies to improve the interface quality is digital etch (DE). DE is a self-limiting etching process that consists of dry oxidation of the semiconductor surface and wet etch of the oxide. This process allows for the accurately scaling down of the fin width and smoothing the sidewalls. Digital etch is also the last process step before the gate oxide is deposited over the fins. It. Therefore, plays a crucial role in surface preparation and holds the key for further improvements to device transport and electrostatics.In this work, we compare the electrical performance of two identical sets of InGaAs FinFETs processed side-by-side that differ only in the type of digital etch that is applied. In one case, the oxide removal step was accomplished using H2SO4, in the other, HCl was used. The starting material consists of 50 nm thick (HC) moderately-doped InGaAs channel layer on top of InAlAs buffer (both lattices matched to InP), as shown in Figure 1(a). Fins are first patterned using E-beam lithography and RIE etched. After this, four cycles of digital etch are applied. Then, the gate dielectric composed of 3 nm HfO2 is deposited by Atomic Layer Deposition. and Mo is sputtered as gate metal and patterned by RIE. In this process, the HSQ that defines the fin etch is kept in place. This makes our FinFETs double-gate transistors with carrier modulation only on the fin sidewalls. The device is finished by via opening and ohmic contact and pad deposition. Transmission Electron Microscopy (Figure 1(b)) is used to verify that the fin shape and dimensions are similar in both samples.Well-behaved characteristics and good sidewall control are obtained in both types of devices. There are a few notable differences. In the OFF state, the HCl sample shows lower gate leakage but larger subthreshold swing compared to the H2SO4 sample (Figure 2(a)). This suggests that HCl treatment results in a higher interface state density (Dit) toward the valence band. In the ON state, however, the intrinsic transconductance, gm,i, exhibits a peculiar trend. For wide fins, the HCl sample shows higher performance but in very narrow fins (Wf<20 nm), H2SO4 performs better (Figure 2(b)). This implies that HCl yields a higher mobility but lower carrier concentration at comparable overdrive. For aggressively scaled fins, the carrier concentration in the fin becomes comparable to Dit, and, as a result, the intrinsic gm of H2SO4 sample (with a lower Dit toward the conduction band) prevails.

Transconductance Dispersion in InGaAs MOSFETs

InGaAs is a promising n-channel material candidate for future CMOS technology due to its superior electron transport properties and low voltage operation. Due to the lack of good native oxide, it has been challenging to achieve a high-quality gate stack, which includes the gate oxide as well as the oxide/semiconductor interface. Many have observed hysteresis and threshold voltage instability in InGaAs MOSFETs that are attributed to interface and oxide defects. In this work, we study the frequency dispersion of InGaAs MOSFETs, an import-ant electrical parameter that is also affected by gate stack defects. The InGaAs MOSFETs used in this study are fabricated in a contact-first, gate-last self-aligned manner. Figure 1 shows the device schematic. The intrinsic channel consists of 8 nm-thick In0.7Ga0.3As. The gate insulator is a 2.5 nm-thick HfO2, deposited by Atomic Layer Deposition (ALD) at 250oC. The gate metal Mo is 35 nm thick, deposited by evaporation. These devices show state-of-the-art performance. We have carried out frequency-dependent electrical characterization from DC to 10 GHz. For the frequency range between 100 kHz and 10 MHz, we employ a lock-in setup and measure the AC drain current induced by AC gate voltage. For frequency range from 100 MHz to 10 GHz, the device S-parameters are measured using a vector network analyzer. From these measurements, we extract the intrinsic transconductance, gm,i. Figure 2 (a) shows the frequency dispersion of the intrinsic transconductance (gm,i) from DC to 10 GHz. As AC frequency increases, deep-level trap states can no longer respond, and device performance improves. gm,i increases from 775 mS/mm to 2200 mS/mm from DC to 10 GHz. The dispersion throughout the entire frequency range also indicates defect states with different time constants. It is remarkable how much unrealized intrinsic performance is left at DC. Figure 2 (b) shows peak gm,i at 10 GHz as a function of gate voltage. Here it is clear that the higher the gate voltage, the larger the gap between DC and 10 GHz gm,i. At the highest gm,i, the ratio is about a factor of 3.In conclusion, we have found large frequency dispersion of intrinsic transconductance in InGaAs MOSFETs, leading to a compromised device performance at DC. Thus, it is important to mitigate the oxide and interface defects in order to unveil the intrinsic outstanding transport properties of InGaAs.

Vertical Gallium Nitride Power Transistors

Lateral and vertical gallium nitride (GaN)-based devic-es are excellent candidates for next-generation power electronics. They are expected to significantly reduce the losses in power conversion circuits and enhance the power density. Vertical GaN devices can achieve high-er breakdown voltage (BV) and handle higher current/power than lateral GaN devices and are therefore prom-ising for high-voltage and high-power applications. The development of vertical GaN power transistors has been hindered by the need to perform epitaxial regrowth or dope the layer p-type. The epitaxial regrowth greatly increases the complexity and cost of device fabrication. p-type GaN has low ratio for the acceptor activation, memory effects, and much lower carrier mobility compared to that in n-GaN.We demonstrate a novel normally-off vertical GaN power transistor with submicron fin-shaped channels. This vertical fin transistor only needs n-GaN layers, with no requirement for epitaxial regrowth or p-GaN layers (Figure 1). A specific on-resistance of 0.2 mΩ·cm2 and a BV over 1200 V have been demonstrated, with a threshold voltage of 1 V rendering normally-off operation (Figure 2). These results set a new record performance for 1200-V class power transistors and demonstrate the great potential of vertical GaN fin power transistors for high-power applications.

Vertical Gallium Nitride Power Diodes on Silicon Substrates

Vertical gallium nitride (GaN) devices are excellent can-didates for next-generation power electronics. How-ever, their commercialization has been hindered so far by the high cost and small diameter of GaN substrates. GaN vertical devices on low-cost silicon (Si) substrates are therefore highly desired, as they could allow for at least 50-to-100-fold lower wafer and epitaxy costs as well as the possibility of processing on 8-inch Si substrates. However, the insulating buffer layers typically found on GaN-on-Si wafers make it challenging to realize vertical current conduction.Since 2014, we have developed three generations of vertical GaN-on-Si power diodes. The first generation utilized a quasi-vertical structure, where the anode and cathode are placed on a mesa step on the same wafer side (Figure 1(a)). We then demonstrated fully-vertical diodes by flip-chip-bonding the GaN-on-Si wafer to another Si wafer followed by the removal of insulating buffer layers. Recently, a novel technology was developed for making fully-vertical diodes (Figure 1(b)). Si substrate and buffer layers were selectively removed, and the bottom cathode was formed in the backside trenches. A specific differential on-resistance of 0.35 mΩ·cm2 and a breakdown voltage of 720 V were both demonstrated (Figure 2), setting a new record performance in all vertical GaN power diodes on foreign substrates.

Vertical GaN Transistors for RF Applications

Stemming from their high breakdown voltages, large power densities, and high efficiency, GaN devices have quickly grown in popularity over the last two decades. With uses in millimeter wave applications like radar, satellite communication, and electronic warfare, the ev-er-increasing demand for high power devices that oper-ate over large bandwidths requires that new transistor technology is created. Since vertical device dimensions and doping can be carefully controlled during wafer growth, a vertical design is ideal for RF devices which need short gate lengths. Moreover, by utilizing the ver-tical dimension, we can achieve excellent power density at millimeter-wave frequencies with minimal die area, and since most transport occurs through the bulk of the material, we also expect thermal management and reliability improvements when compared to the tradi-tional GaN high electron mobility transistor (HEMTs). In this project, we adopt the design of recently devel-oped vertical GaN transistors, which were initially op-timized for high power applications, and modify them for improved RF performance. Another important benefit of a vertical fin design is the ability for threshold voltage engineering. In RF devices, an important metric to non-linearity is g m’’ (the second derivative of device transconductance), which is ideally flat. One method for correcting this is through threshold voltage engineering where devices of varying VT are connected in parallel. Since shifting V T also shifts the peaks of gm’’, with careful design, the peaks of one transistor’s gm’’ can effectively cancel those of another when superimposed. The resultant device will then have a flatter transconductance response with improved RF performance. Through the fin-based design of the transistors in this project, the transconductance can be adjusted by simply altering the width of each fin, thus allowing for optimized large signal response for RF applications. At MTL, we are fabricating the first vertical GaN fin RF transistors. For this, we are using electron beam lithography paired with a combination of dry and wet etching to achieve 100-300 nm tall fins with very smooth and vertical sidewalls. A molybdenum gate allows for a well-controlled etch-back process which coats only the sidewalls in metal. Further dry/wet etching can then be used to access the highly doped drain layer, which was defined during wafer growth. With the gate, source, and drain all on the top surface, this design will be compatible with GaN on Si technology, capable of significantly reducing material costs.

High-temperature GaN Technology

Gallium nitride (GaN)-based transistors are very prom-ising candidates for high power applications due to their high electron mobility and high electric break-down field. Compared to conventional Si or GaAs based devices, wide bandgap GaN also has fundamental ad-vantages for high-temperature applications thanks to their very low thermal carrier generation below 1000°C. However, in spite of the excellent performance shown by early high-temperature prototypes, several issues in traditional lateral AlGaN/GaN HEMTs could cause ear-ly degradation and failure under high-temperature op-eration (over 300°C). These include ohmic degradation, gate leakage, buffer leakage and poor passivation. In addition, to enable digital circuits, it is critical to have enhancement-mode HEMTs, while two-dimensional electron gas induced by AlGaN/GaN heterostructure makes HEMTs be natural depletion-mode devices. In this work, we are developing a new GaN technology for high-temperature applications (>300°C). For this, we are first increasing the temperature stability of the ohmic contacts in GaN HEMTs, by combining a refractory metal such as tungsten (W) with Si-ion implantation, which locally dopes the material n-type and reduces the contact resistance. The schematic cross section is shown in Figure 1. An R c of 0.8 Ω mm, I max of 700 mA/mm were obtained with the W ohmic contacts in a transistor with a gate length of 4 µm. The W ohmic contacts were stable at least up to 300°C in air for at least 30 min, as seen in Figure 2, while conventional alloyed Ti/Al/Ni/Au ohmic contacts showed a strong temperature dependence and their contact resistance increased from 0.47 Ω mm (RT) to 2.15 Ω mm (300°C).Gate injection transistors (GIT) have also been studied for enhancement-mode HEMTs. The structure used in this work had a 110nm extra p-GaN layer on 15nm Al0.2Ga0.8N barrier layer to fully deplete 2DEG under gate area. As shown in Ids-Vgs in Figure 3, a positive VT around 3V was achieved, and their high-temperature stability is currently under investigation.

Novel GaN Transistor Design for High Linearity Applications

Enhancing the linearity of Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) is essen-tial for future RF applications that require extremely low intermodulation distortion and gain compres-sion. In this project, we have studied the origins of non-linearities in GaN-based amplifiers and propose device-level solutions to improve linearity. First, the drop in transconductance (gm) at high current levels observed in GaN transistors can be mitigated with ei-ther self-aligned or finFET-like structures. This is due to the higher current-driving capability of the source access region on these devices. The second cause of de-vice non-linearity has been linked to the large second derivative of the transconductance with respect to gate-source voltage (Vgs) (gm”). This can be overcome by using a new generation of engineered finFET tran-sistors where the width of each fin is optimized for minimizing gm” [3]. In addition, the non-linear behavior of the device capacitances with operating voltage also plays a very important role in device non-linearities. In this case, too, nanostructures can be used to improve device performance. Finally, memory effects due to sur-face and buffer trap also contribute to non-linearities in amplifiers, and they can also be overcome through the use of nanostructures.

Sub-micron p-Channel GaN Tri-gate MISFET

Remarkable attributes of GaN has led to the develop-ment of transistor technology for both power electron-ics and RF applications. Even though much attention is given to n-channel GaN transistor technology, p-chan-nel GaN transistors still lack attention. Development of p-channel GaN transistors is a must to harness the full potential that GaN technology has to offer in achieving high-efficiency power conversion. In this work, we have demonstrated for the first time sub-micron p-channel tri-gate MISFET with fin width of 200 nm. Figure 1(a) shows the schematic of fabricated device structure along with device dimensions. Figure 1(b) and 1(c) show the SEM image of the final device and the fins respectively. Because of the relatively thin AlGaN layer, the measurement results show significant electron contribution to the total drain current. However, if we deduct the current due to 2-DEG at the interface of AlGaN/GaN, we can extract the hole current. Figure 2 shows the IDS-VDS characteristics of the hole current. To prove that the current in Figure 2 predominantly is not because of the holes in the top p-GaN layer rather than the 2-DHG present at the GaN/AlGaN interface, we performed a low-temperature measurement. Because of relatively higher activation energy of Mg (~240 meV) in GaN, the p GaN layer is expected to be frozen out at around 77K leaving only the 2-DHG channel for the hole current. Figure 3 shows the hole current at 80K.

Reliability of GaN High Electron Mobility Transistors

High electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures have been studied in lit-erature for a variety of high-frequency and high-pow-er applications. To minimize lattice mismatch and suppress defects generation, HEMTs, under study, are mostly fabricated on sapphire or SiC substrates. Cur-rently, there is strong interest to fabricate GaN HEMTs on silicon substrates due to its low cost and compatibil-ity with complementary metal–oxide–semiconductor (CMOS) integration technology. However, market adop-tion of this technology is still limited by the HEMT de-vice reliability.We have investigated the effects of SixN1-x passivation density on the reliability of AlGaN/GaN-on-Si HEMTs. Upon stressing, devices degrade in two stages: fast-mode degradation, followed by slow-mode degradation (Figure 1). Both degradations can be explained by different stages of pit formation at the gate edge. Fast-mode degradation is caused by pre-existing oxygen at SixN1-x /AlGaN interface. It is not significantly affected by the SixN1-x density. On the other hand, slow-mode degradation is associated with SixN1-x degradation caused by electric-field-induced oxidation. By using high-density SixN1-x, the slow-mode degradation can be minimized.Devices for research purposes are usually designed and fabricated in a way that certain failure can be magnified to study the failure mechanism better. However, commercial devices focus more on reliability and performance maximization. In ongoing research, we are also interested in characterizing the reliability of commercial GaN HEMTs produced by CREE Inc. A statistical reliability model will be developed, and comparison with devices produced by SMART-LEES will be made. Figure 2 shows the initial characterization of GaN HEMTs produced by CREE, Inc. Reliability testing of these devices is underway.

Dielectric Breakdown in a Novel GaN Power Field-effect Transistor

Gallium Nitride (GaN) transistors are increasing in pop-ularity for high voltage power electronics applications. The most promising device structure is the metal-insu-lator-semiconductor high electron mobility transistor (MIS-HEMT). MIS-HEMTs are of interest because of their high breakdown voltage, low gate leakage cur-rent, and high channel conductivity. However, before commercial deployment, more work is required to improve the reliability and to reduce the instability of GaN MIS-HEMTs (Figure 1). Our work is focused on the characterization, ON-state time-dependent dielectric breakdown (TDDB), OFF-state TDDB, and Weibull sta-tistical analysis of a novel GaN transistor. Our goal is to study and understand the physics behind gate dielec-tric breakdown in this device in order to assess device robustness to prolonged operation. We have complet-ed many studies on these devices to determine break-down location along the channel, chip to chip variation, temperature dependence, voltage dependence, thresh-old voltage shift, and projected lifetime.During sustained ON-state bias at a high voltage, these devices exhibit trapping effects, stress-induced leakage current (SILC), progressive breakdown and eventually, hard dielectric breakdown (Figure 2). This is comparable to past MIS-HEMT studies in our group. As expected, hard breakdown time decreases as both temperature and drain voltage (VDS) are increased.OFF-state TDDB proved difficult because of parasitics, test implementation, and a high variability of over three orders of magnitude in hard breakdown time. An alternative methodology was used, increasing VDS in a linear ramp until hard breakdown occurred. This allows us to characterize the instantaneous breakdown voltage of the devices. Analyzing these results using a Weibull distribution shows a two-slope distribution. This can mean that two breakdown mechanisms are present or that there are multiple layers in the gate stack with different rates of defect generation.Our present research focuses on determining a methodology to accurately evaluate device lifetime during the application of a large drain bias while the device is in the OFF state.

Gate Dielectric Reliability under Mechanical Stress in High-voltage GaN Field-effect Transistors

Energy-efficient electronics have been gaining atten-tion as a solution to meet the growing demand for ener-gy and sustainability. GaN field-effect transistors (FET) show great promise as high-voltage power transistors due to their ability to withstand a large voltage and car-ry large current. However, at the present time, the GaN metal-insulator-semiconductor high-electron-mobili-ty-transistor (MIS-HEMT), the device of choice for elec-tric power management, is limited from commercializa-tion due to many challenges, including gate dielectric reliability. Under continued gate bias, the dielectric ultimately experiences a catastrophic breakdown that renders the transistor useless, a phenomenon called time-dependent dielectric breakdown (TDDB).One key issue is the impact of mechanical strain on TDDB. In particular, when studying OFF-state stress conditions where the drain-source bias is very positive and gate-source bias is negative, the presence of unknown traps at both the interfaces and the bulk of the heterolayers can detrimentally impact dielectric reliability. Mechanical strain introduced during fabrication steps may be causing further reliability problems by amplifying the presence of traps.To understand the impact of mechanical strain on TDDB, we apply external strain by physically bending the devices. We compare the TDDB distributions which follow the Weibull statistical distribution at different external strain.Figure 1 shows TDDB under ON-state stress conditions. Under this situation, the gate is held at a positive bias while the drain and the source are grounded. Since the channel is not depleted, the electric field across the dielectric is distributed throughout the entire gate length and therefore traps make minimal impact on TDDB. Indeed, the breakdown statistics show that for two different mechanical strain, there is little change.On the other hand, figure 2 shows that TDDB under OFF-state stress condition changes with external strain. Under this stress condition, the majority of the electric field through the dielectric is focused at the gate/drain edge. As more of the electric field is focused in a small area, traps can play a significant role in TDDB.Understanding the role of mechanical stress in amplifying trap effects will help the efforts to understand the physics behind TDDB.

High-performance Graphene-on-GaN Hot Electron Transistor

Hot electron transistors (HETs) are promising devices for high-frequency operation and probing the fun-damental physics of hot electron transport. In a HET, carrier transport is out of plane (Figure 1) due to the injection of hot electrons from an emitter to a collec-tor which is modulated by a base electrode. HETs have been used to probe scattering events, band nonparabo-licity, size-quantization effects, and intervalley trans-fer in different material systems. Monolayer graphene, being the thinnest available conductive membrane in nature, provides us with the opportunity to study the HET transport properties at the ultimate scaling limit. Previously, we have demonstrated graphene-base HET with GaN/AlN emitter and a graphene/WSe2 van der Waals heterostructure collector base-collector stack that can overcome the performance limitation of the graphene-base HETs with oxide barriers. In this work, we studied the effect of material parameters on the transport properties of the heterojunction diodes (i.e., Emitter-Base and Base-Collector) of HETs, and their impact on the HET performance. Temperature dependent transport measurements identify quantum mechanical tunneling as the major carrier transport mechanism in HETs. We demonstrate a new generation of graphene-base HET with record current density above kA/cm2 (Figure 2) by scaling the tunneling barrier thickness and device geometry optimization. Preliminary simulations show that with further optimization graphene-on-GaN HET can outperform the bulk HETs towards ultra-high frequency operation.

Circuit-performance Evaluation of Negative Capacitance FETs using MIT Virtual Source Negative Capacitance FET (MVSNC) Model

Negative Capacitance Field Effect Transistors (NCFETs) have emerged as promising candidates for CMOS tech-nology scaling due to their potential for sub-60-mV/de-cade operation by utilizing negative capacitance effects in ferroelectric materials. A ferroelectric oxide (FE-ox-ide) capacitor in series with the normal gate-stack ca-pacitor of a conventional MOSFET forms the NCFET as shown in Figure 1. A physics-based compact model, MVSNC, is proposed to capture the device–behavior under static and dynamic operating conditions using the MVS-framework for the underlying MOSFET and the Landau-Khalatnikov (L-K) equation to model the FE-oxide as shown in sub-circuit of Figure 1.The baseline MOSFET is characterized against Intel-45nm data and while PZT oxide of tFE=5 nm is chosen for NCFETs. The model is implemented in Verilog-A, and transient simulations are performed using a commercial simulator (ADS®). The simulated device-level IV- and CV-characteristics of NCFET and baseline FET are shown in Figure 1. With same off-currents, NCFETs exhibit steep subthreshold-swing (SS) due to stabilization of negative capacitance (NC)-state in FE-oxide and VG,int-amplification compared to VG. Higher on-current (at same VG) with reduced or negative DIBL at certain VD regimes can also be seen. The CV-characteristics show capacitance-amplification in sub-threshold regime. Leakage in FE-oxide that can potentially remove the SS-steepness advantage in NCFETs is studied along with work-function engineering (WFE) that is proposed to mitigate the impact of FE-leakage. By shifting the FE-oxide’s Q-V curves along voltage-axis, WFE allows NC-state to be reached at low-VDD. The energy-delay (E-td) figure-of-merit of the NCFETs can be compared against baseline CMOS using loaded ring-oscillator (RO)-simulations. 21-stage ROs loaded with a constant capacitance CL whose value is equal to total on-capacitance (CGG at VD=0 and VG=1V) of the constituent baseline FETs of inverter are shown in Figure 2. Here, VDD is swept to get the energy-delay plot. The figure shows reduced E-td in NCFETs even under leakage because of lower switching loss in CL (0.5CLV2DDf). The benefit of lower E-td with NCFETs is significant at scaled VDD nodes and can be preserved even under DE-leakage scenarios by adopting WFE.

Negative Capacitance Carbon Nanotube Field-effect Transistors

As continued scaling of silicon field-effect transistors (FETs) grows increasingly challenging, alternative paths for improving digital system energy efficiency are actively being pursued. These paths include replacing the transistor channel with emerging nanomaterials (such as carbon nanotubes: CNTs), as well as utilizing negative capacitance effects in ferroelectric materials in FET gate stacks, e.g., to improve sub-threshold slope beyond the 60 mV/decade limit (at temperature = 300 °K) for conventional FETs (which in itself is difficult to achieve due to short-channel effects). However, which path provides the largest energy efficiency benefits, and whether these multiple paths can be combined to achieve additional energy efficiency benefits, is still un-clear. Here, we experimentally demonstrate the first negative capacitance carbon nanotube FETs (CNFETs: Figure 1), combining the benefits of both carbon nanotube channels (which offer superior electrostatic control vs. silicon-based FETs, simultaneously with superior carrier transport) and negative capacitance effects. We experimentally demonstrate negative capacitance CNFETs (NC-CNFETs) that achieve sub-60 mV/decade sub-threshold slope. Across 50 NC-CNFETs, our experimental results show an average sub-threshold slope of 55 mV/decade at room temperature, compared to 70 mV/decade for baseline CNFETs, i.e., without negative capacitance (Figure 2). The average on-state drive current (ION) of these NC-CNFETs improves by 2.1× vs. baseline CNFETs, for the same off-state leakage current (IOFF). This work demonstrates a promising path forward for future generations of energy-efficient electronic systems.

MoS2 FETs with Doped HfO2 Ferroelectric/Dielectric Gate Stack

Atomically thin layered two-dimensional transition metal dichalcogenides such as molybdenum disulfide (MoS2) have been proposed to enable aggressive minia-turization of FETs. We previously reported ultra-short channel MoS2 FETs with channel length down to 15 nm and 7.5 nm using graphene and directed self-assembly pattern technique, respectively. However, the power scaling in such devices suffers from the same issues as in CMOS technology. Obtaining a subthreshold swing (SS) below the thermi onic limit of 60 mV/dec by exploiting the negative-ca pacitance (NC) effect in fer-roelectric (FE) materials is a novel effective technique to allow for the reduction of the supply voltage and power consumption in field-effect transistors (FETs). Conventional ferroelectric materials, i.e., lead zirconate titanate, bismuth ferrite, and polymer ferroelectric di-electrics such as P(VDF)-TRFE are not technologically compatible with standard CMOS fabrication process-es. On the other hand, fluorite-type doped HfO2 ferro-electric thin-films deposited by ALD offers the CMOS compatibility and scalability required for advanced electronic applications. In this work, we demonstrate NC-MoS2 FETs by incorporating a ferroelectric doped HfO2 (Al:HfO2 or Si: HfO2 ) in the FET gate stack. Standard HfO2 has monoclinic crystal structure which can be transformed into orthorhombic phase by temperature, pressure, or doping. The electrical properties of the doped HfO2 thin-films can be tuned from dielectric to ferroelectric and even antiferroelectric by changing dopant type (Zr, Al, Si, Gd, Y, etc.), dopant fraction and/or capping layer. The ferroelectric nature of typical doped HfO2 thin film can be confirmed by the polarization measurement (Figure 1). Here, Si:Hf composition is kept fixed by controlling the 3DMAS/TEMAH pulses during the ALD. We observe steep SS in FETs when used these FE in the gate stack with carefully matched FE/DE bilayer. The NC-MoS2 FET built on a typical FE/DE bilayer showed a significant enhancement of the SS to 57 mV/dec at room temperature, compared with SSmin = 67 mV/dec for the MoS2 FET with only HfO2 as a gate dielectric.

Graphene-based Ion-sensitive Field-effect Transistor Sensors for Detection of Ionized Calcium

Ion-sensitive field-effect transistors (ISFET) are used for measuring ion concentration in solution. Typical ISFET is silicon-based and suffers stability problems. Graphene is an atomically thin material with excellent electrical, mechanical, optical, and chemical properties. It can be used to replace silicon for biological and chem-ical sensing with the potential of being light weighted, flexible, and transparent. This work develops a sensing platform (Figure 1A) with 152 individual ISFETs and an automatic data acquisition system. The array is functionalized with an ion-selective membrane and acts as a calcium sensor with excellent selectivity, sensitivity and response time. In particular, only calcium ion can be transported from the solution phase into the membrane via a charge neutral ionophore. At equilibrium, a stable Nernstian interface potential is achieved. With higher calcium concentration, the interface potential increases causing an effective shift in the sensor I-V characteristic. Hence, the sensor can detect and quantify changes in ionized calcium concentration through the shift in sensors I-V characteristic.The shift in I-V characteristic is quantified by the location of minimum conduction point in graphene’s V-shaped curve, Dirac point. The theoretical rate of change in potential versus calcium concentration at room temperature is approximately 30mV/decade for bivalent ions such as calcium. Our data shows an average slope of 30.1 mV/decade with a standard deviation of 1.9 mV/decade, which agrees very well with the theory, therefore, indicates excellent sensitivity. By matching data from transient response with data from I-V characteristic, we can calculate the concentration of calcium with a single calibration reference. As depicted in Figure 1C, sensors are capable of quantifying ionized calcium concentrations spanning over five orders of magnitude. This proof-of-concept work represents a milestone in the development of graphene-based sensors for solution-phase chemical detection of analytes such as ionized calcium.

High Breakdown Voltage in Solution-processed High-voltage Organic Thin Film Transistors

Organic thin film transistors (OTFT) are excellent can-didates for large area electronics on arbitrary and flex-ible substrates, enabling novel flexible displays as well as wearable electronics such as artificial skin. However, enabling truly-ubiquitous electronics through OTFTs demands not only high performance and high degree of flexibility, but also a wide range of operating voltag-es. Applications such as electrophoretic displays, digi-tal X-ray imaging, photovoltaic systems-on-glass, and TFT-MEMS integration for large actuation are but a few that can enable high driving voltages on an OTFT technology platform.We are currently developing a solution-processed 6,13-Bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) high-voltage, organic, thin film transistor (HVOTFT) with self-assembled monolayer (SAM) treatments that is capable of driving voltages beyond -450 V while operating with threshold voltages below -10 V. The ability to modulate such high-voltages with a relatively low gate voltage is highly appealing for future MEMS integration. The HVOTFT is defined by a dual channel architecture comprised of a gated and offset region, enabling FET and high-voltage capabilities, respectively. Furthermore, a high-k cubic pyrochlore dielectric Bi1.5 Zn1Nb1.5O7 (BZN) is employed to achieve low gate leakage currents and low threshold voltages.A combination of organosilane self-assembled monolayers and a self-shearing drop cast method is used to grow thin (< 100 nm) crystal bands of TIPS-pentacene on the HVOTFT structures. Controlling the thickness of the organic semiconductor layer is critical in achieving high breakdown voltages of -450 V as well as high ION/IOFF current ratios of 104 A/A. Recent efforts in developing a self-aligned solution-process using surface energy engineering to enhance control of the crystal growth as well as to have transistor-to-transistor isolation have proven promising.

Characterization of Room-temperature Processed Thin Film Capacitors under Curvature

Organic thin film transistors (TFTs) have been of great interest lately because of their potential applications in flexible systems, enabling devices such as electronic skins or implantable medical devices. With the ability to bend these new systems comes the question of how bending affects device perform. Consequently, thicker oxide layers are desirable because they are less likely to be stretched thin when flexed, preventing tunneling processes and high leakage currents. High-k dielectrics, such as the cubic pyrochlore Bi1.5Zn1Nb1.5O7 (BZN), have the potential to improve the reliability of this technol-ogy because they allow for a thicker film without de-creasing capacitive coupling.In this work, we investigated how the operating characteristics, like capacitance, change when devices are flexed. When the BZN is bent, strain is introduced into the crystal structure which can affect the dielectric constant. To explore this, we fabricated MIM capacitors and measured capacitance at different degrees of curvature to extract the dielectric constant. The capacitors, shown in Figure 1, were fabricated with a reactive sputtered BZN. Frequently, BZN is annealed at temperatures of 500-700°C; however, many flexible substrates, such as the Kapton polyimide films used here, are not compatible with such high-temperatures. Without annealing, the BZN was amorphous with a dielectric constant of around 30 as compared to values up to 200 found in crystalline BZN.We found that when the devices were bent to the radii of curvature shown in Figure 2, the capacitance dropped to 85-95% of the original capacitance when flat. As there was no apparent change in thickness or area of the devices, we’ve attributed this to a change in dielectric constant caused by strain in the crystal structure altering the alignment of electric dipoles in the material. When the devices were again laid flat, the capacitance returned to 95-99% of the original value. The information found in the MIM capacitor could be used to infer how device bending would affect behavior of a BZN-based OTFT for flexible applications.

Room Temperature Spin-orbit Torque Switching Induced by a Topological Insulator

Recent studies on the topological insulators (TI) have attracted great attention due to the rich spin-orbit physics and promising applications in spintronic de-vices. In particular, the strongly spin-moment coupled electronic states have been extensively pursued to re-alize efficient spin-orbit torque (SOT) switching. How-ever, so far current-induced magnetic switching with TI has been observed only at cryogenic temperatures. Whether the topologically protected electronic states in TI could benefit from spintronic applications at room temperature remains a controversial issue.In this work, we report SOT switching in a TI/ferromagnet heterostructure with perpendicular magnetic anisotropy (PMA) at room temperature. Ferrimagnetic cobalt-terbium (CoTb) alloy with robust bulk PMA is directly grown on a classical TI material, Bi2Se3. The low switching current density provides definitive proof of the high SOT efficiency from TI and suggests the topological spin-momentum locking in TI even if it is neighbored by a strong ferromagnet. Furthermore, the effective spin Hall angle of TI is determined to be several times larger than commonly used heavy metals. Our results demonstrate the robustness of TI as an SOT switching material and provide an avenue towards applicable TI-based spintronic devices.

Current-induced Domain Wall Motion in Compensated Ferrimagnets

Antiferromagnetic materials show promises compared to ferromagnetic materials for spintronic devices due to their immunity to external magnetic fields and their ultra-fast dynamics. However, difficulties in controlling and determining their magnetic state are limiting their technological applications. At the compensation point, the two antiparallel sub-lattices in a ferrimag-net have the same magnetic moment, and the materi-al is an antiferromagnet. Compensated ferrimagnets are expected to exhibit fast magnetic dynamics like an antiferromagnet, and yet their magnetic state can be manipulated and detected like a ferromagnet, and therefore, have been pursued as a candidate system for ultrafast spintronic applications. Previously, it was demonstrated that current-induced spin-orbit torque could provide an efficient switching mechanism for a compensated ferrimagnet. However, limited by the quasi-static measurement technique, the nature of the switching dynamics in these experiments is yet to be revealed. In this work, we provide the first experimen-tal proof of current-induced fast domain wall (DW) mo-tion in a compensated ferrimagnet.Using a magneto-optic Kerr effect microscope, we determine the spin-orbit torque-induced DW motion in Pt/Co1-xTbx microwires with perpendicular mag-netic anisotropy. The DW velocity is determined as a function of applied current amplitude. A large en-hancement of the DW velocity is observed in angular momentum compensated Pt/Co0.74Tb0.26 microwires compared to single layer or multi-layer ferromagnetic wires (Figure 1). Using analytical model, we also find that near angular momentum compensation point, the domain walls do not show any velocity saturation unlike ferromagnets or uncompensated ferrimagnets since both the effective gyromagnetic ratio and effec-tive damping diverge at this composition (Figure 2). Moreover, by studying the dependence of the domain wall velocity with the longitudinal in-plane field, we identify the structures of ferrimagnetic domain walls across the compensation points. The high current-induced domain wall mobility and the robust domain wall chirality in compensated ferrimagnets open new opportunities for spintronic logic and memory devices.

Research on CMOS-compatible High-k Dielectrics for Magneto-ionic Memory

High-k dielectrics play a key role in modern microelec-tronic circuitry, given their ability to provide reduced leakage currents while providing adequate capacitance in ever smaller nano-dimensioned metal-oxide semi-conductor field-effect transistor (MOSFET) devices. Re-cently, the Beach group at MIT demonstrated the ability to modulate the magnetic properties of transition met-al thin films by electrical bias across thin films of Gd2O3. The reversible switching was demonstrated to be assist-ed by the electro-migration of oxygen ions to and away from the transition metal/Gd2O3 interface. This novel process, now called “magneto-ionic control” creates new opportunities for nonvolatile information storage. Like magneto-ionic device, there is another important emerging device called “memristor” which applies field driven ionic transport-controlled property toggling. Though this device has been researched widely for a decade and defect chemistry of dielectrics is critical to the device operation, understanding of defect chemistry of dielectrics used for memristors are still limited. Here, we have examined electrical and transport properties of Gd2O3 via impedance spectra as a function of temperature and oxygen partial pressure considering Gd2O3 as a model oxide for ionic migration-controlled devices. In this research, we found that Gd2O3 can be electronic or mixed ionic-electronic conductor at high-temperature via controlling doping and phase. This research will be continued to the lower temperature regime to understand the correlation between the behavior of such devices and defect chemistry of dielectrics.In addition, we have begun an investigation of the mechanism of magneto-ionic devices in a viewpoint of considering magneto-ionic device as an electrochemical cell. Previous research indicated that this device behaves in a manner similar to high-temperature electrochemical devices. We are preparing model devices that reflect features of both magneto-ionic and electrochemical devices and are examining their properties in situ.

Probing 2-D Magnetism in van der Waals Crystalline Insulators via Electron Tunneling

In this work, we introduce tunneling through layered insulators as a versatile probe of nanoscale magnetism. We fabricate van der Waals heterostructures of two graphite sheets separated by a magnetic CrI3 tunnel barrier (Figure 1). For magnetic tunnel junctions, the barrier height is lowered for electrons aligned with the magnetic layer, resulting in a direct dependence of the conductance across the junction on the magnetic or-dering in the CrI3 barrier.Layers of CrI3 align their spins perpendicular to the crystal, either up or down. By sweeping an applied magnetic field, we detect discrete steps in the junction conductance (Figure 2) corresponding to individual layers in the CrI3 barrier flipping out-of-plane magnetization. For example, when the magnetic field is swept up past 1 T in the bilayer device, the spins in the two layers of CrI3 both align with the field, resulting in a 95% magnetoresistance.Moreover, we can control the spin polarization of the output current with applied magnetic field, generating currents with up to 99% polarization. Thus, in addition to studying 2-D magnetic crystals using electrical readout of the magnetization, this result could also be applied to develop novel magnetic memory devices incorporating spin-orbit torques and other spintronic techniques.

Microwave Modulation of Relaxation Oscillations in Superconducting Nanowires

Superconductors are ideal platforms for studying non-linear behavior due to their nonlinear switching dy-namics and phase relationships. Josephson junctions (JJs), the most common superconducting devices, have a nonlinear current-phase relationship that allows them to phase lock to weak external periodic drives. This phenomenon, known as the AC Josephson effect, produces distinct DC steps in the time-averaged cur-rent-voltage characteristics at voltage intervals of Vn = nhf/2e, where n is an integer, h is Planck’s constant, f is the frequency of the external radiation, and e is the electronic charge. Such a relationship has enabled tech-nology such as the Josephson voltage standard and an-alog-to-digital converters.Unlike JJs, superconducting nanowires are governed by a thermal nonlinearity that controls the switching into and out of the resistive state. In this work, we have studied fast oscillations in superconducting nanowires based on the electrothermal feedback between the nanowire hotspot and an external shunt resistor with a series inductance. In addition to studying how circuit parameters influence the frequency of the oscillations, we show that the oscillations can mix with an external microwave drive and eventually phase lock (Figure 1). This process produces a nanowire analog to the AC Josephson effect, with steps occurring at intervals of Vn = nfIcL, here n is an integer, f is the frequency of the drive, Ic is the critical current of the nanowire, and L is the series inductance (Figure 2). In addition to offering a potential avenue for measuring inductance through the appearance of phase-locked steps, the ability of these oscillations to mix with an external drive is promising for applications such as parametric amplification and frequency multiplexing.

A Superconducting Nanowire Based Memory Cell

The development of a practical supercomputer relies on having a scalable memory cell, energy efficient con-trol circuitry, and the ability to read and write a state without sacrificing density. Typical superconducting memories relying on Josephson junctions (JJs) have demonstrated extremely low power dissipation (10-19 J) and rapid access times (< 10 ps), but suffer from large device dimensions and complex readout circuitry, mak-ing scalability a considerable challenge.As an alternative to JJ-based superconducting memories, we have made a memory based solely on lithographic niobium nitride nanowires. The state of the memory is dictated by persistent current stored in a superconducting loop, while the write and read operations are facilitated by nanowire cryotron devices patterned alongside the memory loop in a single lithographic process. In addition to ease of fabrication, superconducting nanowires offer the advantage of relying on kinetic rather than geometric inductance, allowing the memory cell to be scaled down for high device density without sacrificing performance. Additionally, since persistent current is stored without Ohmic loss, the memory cell has minimal power dissipation in the static state.We have demonstrated a 3 µm x 7 µm proof-of-concept device with an energy dissipation of ~ 10 fJ and a bit error rate < 10-7. Current work focuses on developing a multilayer fabrication process to expand the single memory element into an array and to reduce device dimensions for further density optimization.

Novel Device (Resistive Switching Device, Memristor) Structure for Neuromorphic Computing Array

Although several types of architectures combining memories and transistors have been used to demon-strate artificial synaptic arrays, they usually present limited scalability and high-power consumption. Ana-log-switching devices may overcome these limitations, yet the typical switching process they rely on, forma-tion of filaments in an amorphous medium, is not eas-ily controlled and hence hampers the spatial and tem-poral reproducibility of the performance.Here we demonstrate single-crystalline SiGe epiRAM with minimal spatial/temporal variations with long retention/great endurance, and high analog current on/off ratio with tunable linearity in conductance update, thus justifying epiRAM’s suitability for transistor-free neuromorphic computing arrays. This is achieved through one-dimensional confinement of conductive Ag filaments into dislocations in SiGe and enhanced ion transport in the confined paths via defect selective etch to open up the dislocation pipes. In SiGe epiRAM, the threading dislocation density can be maximized by increasing Ge contents in SiGe or controlling degree of relaxation23, and we discovered that 60 nm-thick Si0.9Ge0.1 epiRAM contains enough dislocations to switch at tens of nanometer scale devices. Our simulation-based on all those characteristics of epiRAM shows 95.1% accurate supervised learning with the MNIST handwritten recognition dataset. Thus, this is an important step towards developing large-scale and fully-functioning neuromorphic-hardware.

Metal Oxide Thin Films as Basis of Memristive Nonvolatile Memory Devices

The design of silicon-based memory devices over the past 50+ years has driven the development of increas-ingly powerful and miniaturized computers with de-mand for increased computational power and data storage capacity continuing unabated. However, fun-damental physical limits are now complicating further downscaling. The oxide-based memristor, a simple M/I/M structure, in which the resistive state can be reversibly switched by application of appropriate volt-ages, offers to replace classic transistors in the future. It has the potential to achieve an order of magnitude lower operation power compared to existing RAM technology and paves the way for neuromorphic mem-ory devices relying on non-binary coding. Our studies focus on understanding the mechanisms that lead to memristance in a variety of insulating and mixed Ionic electronic conductors; thereby providing guidelines for material selection and for achieving improved device performance and robustness.

Lithium Neuromorphic Computing and Memories

Ionically-controlled memristors could allow for the realization of highly functional, low-energy circuit elements operating on multiple resistance states and to encode information beyond binary. The application of a sufficiently high electric field induces a non-volatile resistance change linked to locally induced redox processes in the oxide. State-of-the-art devices operate mainly on O2−, Ag+ or Cu2+ ions hopping over vacancies. Surprisingly, despite their fast diffusivity and stability towards high voltages, lithium solid-state oxide conductors have almost been neglected as switching materials. Our work investigates lithium ionic carrier and defect kinetics in oxides to design material architectures and interfaces for novel Li-operated memristors as alternative memory material. Extensive efforts were devoted to understand the growth of the chosen Li-oxides conductor thin films by Pulsed Laser Deposition (PLD) and to microfabricate model thin film architecture devices. In-house overlithiated pellets of the selected oxides were synthesized and used as PLD targets. Dense, crack-free thin film oxides have been successfully grown on Pt/Si3N4/Si substrates, including multilayer heterostructures of two selected Li-oxide materials. Remarkably, Pt/Li-oxide/Pt structures (Figure 1a and b) show a significant bipolar resistive switching effect with a resistance ratio Roff/Ron~104-105 at beneficial low operation voltages to reduce the footprint at operation (~3V for a non-device lab optimized architecture) (Figure 1a). In addition, sweep rate, thickness, and area dependence studies suggest that the bulk oxide plays a major role in the diffusion of the ionic species for achieving a large and tunable resistance ratio. This phenomenon makes the new investigated Li-oxides novel candidate material as new neuromorphic computing element. In situ Raman Spectroscopy and TEM experiments will shed light on the microstructure and its defects and will allow a better understanding of the underlying physical mechanism of the switching behavior. Also, new routes are explored to modify the lithiation degree of the thin films and would add an extra parameter to tune and alter switching kinetics and resistance retention.

Effects of Line Edge Roughness on Photonic Device Performance through Virtual Fabrication

Silicon photonics has garnered a large amount of in-terest in recent years due to its potential for high data transfer rates and for other, more novel applications. One attractive feature of silicon photonics is its rela-tively seamless integration with existing CMOS fab-rication technologies. That means, however, that it is subject to similar random and systematic variations as are known to exist in CMOS manufacturing processes.One common source of process variation is Line Edge Roughness (LER), which occurs during lithography. Since LER produces random perturbations to the component geometry, it is likely to influence the light-guiding abilities of photonic components and devices subject to LER.We study the effect of LER on the performance of a fundamental component, the Y-branch, through virtual fabrication simulations (Figure 1). Ideally, the Y-branch transmits the input power equal to its two output ports. However, imbalanced transmission between the two output ports is observed when LER is imposed on the Y-branch (Figure 2) depending on the statistical nature (amplitude and correlation length) of the LER. The imbalance can be as low as 1% for small LER amplitudes, and reach up to 15% for large LER amplitudes (Figure 3). These results can be captured as worst-case corner models and included in variation-aware photonic compact models.

Reprogrammable Electro-Chemo-Optical Devices

Photonic devices with programmable properties allow more flexibility in manipulation of light. Recently, sev-eral examples of reconfigurable photonic devices were demonstrated by controlling the local/overall index of refraction in thin films, either by thermally induced phase change in chalcogenides or by intercalation of lithium into oxides. We propose a novel approach for design of reprogrammable photonic devices based on electrochemical modification of ceria-based elec-tro-chemo-optical devices. Previously, it was shown that the refractive index of PrxCe1-xO2-δ (PCO) is a function of oxygen nonstoichiometry, δ that can be controlled electrochemically via closely spaced electrodes in a lateral device configuration. For modified transverse configurations, a PCO thin film on yttrium stabilized zirconia (YSZ) substrate with Transparent Conducting Oxide (TCO) top electrode allows for voltage controlled oxygen exchange. Enhanced spatial resolution can be further achieved with the aid of lithographically patterned nano-dimensioned oxide layers.

On-chip Infrared Chemical Sensor Leveraging Supercontinuum Generation in GeSbSe Chalcogenide Glass Waveguide

In this report, we demonstrate the first on-chip spec-troscopic chemical sensor with a monolithically inte-grated supercontinuum (SC) light source. Unlike tradi-tional broadband, blackbody sources used in benchtop Infrared Radiation (IR) spectrophotometers waveguide SC sources feature high spatial coherency essential for efficient light coupling and manipulation on a photon-ic chip. Compared to tunable lasers, SC offers superior bandwidth coverage. The broadband nature of SC facil-itates access to wavelengths that are difficult to cover using semiconductor lasers, and thereby, significantly expands the identifiable molecule repertoire of spec-troscopic sensors. In our experiment, we use chalco-genide glass (ChG) as the waveguide material for both SC generation and evanescent wave sensing. ChGs are known for its broadband infrared transparency, large Kerr nonlinearity, and low two-photon absorption (TPA), ideal characteristics for our application. 400 nm thick Ge22Sb18Se60 (GeSbSe) films were thermally evaporated onto 4” silicon wafers with 3 µm thermal oxide as an under cladding from GeSbSe glass powders. GeSbSe waveguides with varying length were fabricated using our previously established protocols. In the process, a 350-nm-thick ZEP resist layer was spun onto the substrate followed by exposure on an Elionix ELS-F125 tool at a beam current of 10 nA. The resist pattern was then developed by immersing in ZED-N50 developer for one minute. Reactive ion etching was performed in a PlasmaTherm etcher to transfer the resist pattern to the glass layer. The etching process used a gas mixture of CHF3 and CF4 at 3:1 ratio and 5 mTorr total pressure. The incident Radio Frequency (RF) power was fixed at 200 W.Finally, the device was immersed in N-Methyl-2-pyrrolidone (NMP) overnight to remove the ZEP resist and complete device fabrication. The waveguides assume a zigzag geometry with lengths up to 21 mm. Figure 1a plots the SC spectra in GeSbSe waveguides with the different lengths and the optimal dimensions (W = 0.95 µm, H = 0.4 µm). As indicated in the figures below, the SC bandwidth extends to over half an octave, albeit with decreased total output power when the waveguide length increases to 21 mm. In the sensing experiment, the GeSbSe waveguide was immersed in carbon tetrachloride (CCl4) solutions containing varying concentrations of chloroform (CHCl3). The CCl4 solvent is optically transparent across the near-IR, whereas the C-H bond in chloroform leads to an overtone absorption peak centering at 1695 nm, a wavelength outside the standard telecommunication bands. SC spectra near the chloroform absorption peak obtained with GeSbSe waveguides of different lengths are presented in Figure 1b. The data were normalized to the background (collected in pure CCl4).

Sensing Chemicals in the mid-Infrared using Chalcogenide Glass Waveguides and PbTe Detectors Monolithically Integrated On-chip

Chemical sensors are important for many applications, from sensing explosive residues for homeland security and defense to sensing contaminants in air and water for environmental monitoring. However, the sensors currently used for these purposes are either bulky, not very sensitive, or not able to identify a chemical specifi-cally. Integrated photonic sensors, which include a light source, photonic sensing element, and photonic detec-tor integrated directly on-chip, that can operate in the mid-infrared (MIR) chemical fingerprint region, prom-ise to be small, sensitive, and specific chemical sensors. They achieve this by confining light within waveguides packed into a small area and using the evanescent field that exists outside the waveguides to sense the pres-ence of a chemical through absorption spectroscopy, identifying chemicals by their unique absorption spec-tra. This work focuses on designing and fabricating the first ever MIR integrated sensing element combined with a detector, operating at room temperature.A spiral waveguide design was chosen for the sensing element due to its long interaction length, which improves sensitivity, while still maintaining a small area footprint. Fabrication was done using a double layer electron beam lithography and liftoff technique to reduce the waveguide sidewall roughness, and therefore loss, of the thermally evaporated chalcogenide glass waveguides. The thermally evaporated polycrystalline PbTe detector was deposited directly underneath the waveguide using photolithography and liftoff. This direct integration of the detector with the waveguide improves coupling of light into the detector while also reducing the size, and therefore noise, level of the detector, allowing it to function at room temperature when most MIR detectors need cooling. Figure 1 shows the spiral sensing element and waveguide integrated PbTe detector. The results from sensing methane gas using 3.3 μm light are shown in Figure 2, demonstrating that this integrated sensing element and detector can effectively sense the presence of chemicals using their MIR absorption spectra.

Broadband Low-loss Nonvolatile Photonic Switches Based on Optical Phase Change Materials (O-PCMs)

Optical switching is an essential function in photon-ic integrated circuits. Recently, a new class of devices based on O-PCMs have emerged for on-chip switch-ing. Unlike electro-optic or thermo-optic effects which are minuscule, phase transition in O-PCMs generates huge optical property modulation conducive to ul-tra-compact device architectures. In addition, such phase changes can be non-volatile, exemplified by the transition between amorphous (a-) and crystalline (c-) states in chalcogenide alloys. Despite these attractive features, the performances of existing PCM-based pho-tonic switches are severely compromised by the high optical absorption in traditional O-PCMs.Here we report the design and modeling of a new kind of photonic switches combining low-loss phase change alloys and a “nonperturbative” design to boost the switching performance. On the one hand, we use a low-loss O-PCM for this application: Ge2Sb2Se4Te1 (GSS4T1). Fig 1a and 1b show the optical constants of GSS4T1 compared with traditional PCM Ge2Sb2Te5 (GST225), as measured by ellipsometry. At telecommunication wavelength, the material figure-of-merit, which is defined as index change over extinction coefficient, is 6 times higher. Moreover, the loss of amorphous state GSS4T1 is 0.00017 measured by waveguide cutback method, which is two orders of magnitude lower. On the other hand, the switch design is based on the huge index change of O-PCMs. The basic element is a directional coupler comprised of a bare waveguide (WG1) and a waveguide covered with a PCM strip (WG2). At (a-) state, their indices are matched, and light will be coupler from WG1 to WG2. At (c-) state, due to the large index change of O-PCM, the modal profile will be completely different, and effective index of WG2 will increase a lot so that coupling will not happen. This helps to keep the loss at a low level since light will not travel in WG2 when GSS4T1 is in its (c-) state. Fig 2 and 3 show the state-of-the-art performance of the 1 by 2 and 2 by 2 switches designed by this method.

Chalcogenide Glass Waveguide-integrated Black Phosphorus mid-Infrared Photodetectors

Black phosphorus (BP) is a promising 2-D material that has unique in-plane anisotropy and a 0.3 eV direct bandgap in the mid-IR. However, waveguide integrated black phosphorus photodetectors have been limited to the near-IR on top of Si waveguides that are unable to account for BP’s crystalline orientation. In this work, we employ mid-IR transparent chalcogenide glass (ChG) both as a broadband mid-IR transparent wave-guiding material to enable waveguide-integration of BP detectors and as a passivation layer to prevent BP deg-radation during device processing as well as in ambient atmosphere.Our ChG-on-BP approach not only leads to the first demonstration of mid-IR waveguide-integrated BP detectors, but also allows us to fabricate devices along different crystalline axes of black phosphorus to investigate, for the first time, the impact of in-plane anisotropy on photoresponse of waveguide-integrated devices. The best device exhibits responsivity up to 40 mA/W and noise equivalent power as low as 30 pW/Hz1/2 at 2185 nm wavelength. We also found that photodetector responsivities changed by an order of magnitude with different black phosphorus orientations. This work validates black phosphorus as an effective photodetector material in the mid-IR and demonstrates the power of the glass-on-2-D-material platform for prototyping of 2-D material photonic devices.

An Ultrasensitive Graphene-polymer Thermo-mechanical Bolometer

Uncooled mid-infrared (Mid-IR) detection and imaging technologies are highly desired for night vision, secu-rity surveillance, remote sensing, industrial inspection, medical, and environmental chemical sensing. Tradi-tional mid-IR detection technologies operating at room temperature are all associated with thermal related phenomena that transfer the optical signals into elec-trical signals through changes of temperature on the device. Here we propose and implement a new signal transducing scheme where the energy transfer path is optical-thermal-mechanical-electrical. By combining highly sensitive strain sensors made with percolative graphene nano-flake films synthesized by Marangoni self-assembly method, and the highly efficient polymer opto-thermo-actuators, we were able to demonstrate the proof-of-concept bolometric type mid-IR detectors (Figure 1) that could be more sensitive than state-of-the-art technologies. Two types of photoresponse behaviors were observed in our devices: a gradual change in resistance in terms of temperature (Figure 2(a)), which may be associated with the average overlap area decrease of adjacent nano-flakes; and an abrupt “switch” like response (Figure 2(b)) that is presumably due to the decrease of the number of conduction paths of the percolative film. Microscopic characterizations and theoretical modeling were carried on to understand such behaviors. Theoretical analysis showed that our new technology could be at least one order of magnitude more sensitive than the fundamental limit of existing uncooled mid-IR technologies (Figure 2(c)).

Nanocavity Design for Reduced Spectral Diffusion of Solid-state Defects

The negatively charged nitrogen-vacancy (NV) center in diamond has an electronic spin state that can be optical-ly initialized, manipulated, and measured. Entanglement generation between two spatially separated quantum memories can be generated by coupling them to optical modes. Coupling NV centers to nanophotonic devices such as waveguides and cavities will boost the NV-NV entanglement rate by increasing the emission and collec-tion rate of photons entangled with the spin resonators.We can fabricate 1D photonic crystal nanobeam cavities in diamond with quality factors larger than 16,000. Unfortunately, an optimally coupled NV center in such a cavity will be only 30 nm from surfaces, and the linewidths of NV centers in such cavities is increased to 10s of GHz (1000x the natural lifetime limited linewidth) due to spectral diffusion.To obtain NV centers with GHz linewidths in a cavity with a high-quality factor, we design and fabricate novel “Alligator” cavities. A bandgap is created via a sinusoidal width modulation. A high-Q mode is trapped in a defect created by reducing the amplitude of the modulation. The optimized mode (seen in Figure (a)) has a Q > 100,000 in simulation. We fabricate these cavities from single crystal bulk diamond. A scanning electron micrograph of one is seen in Figure (b). In experiment, we measure cavities with a mean Q value of ~7000 (Figure (d)). Figure (c) shows the spectrum of such a cavity. These structures should allow coupling between single NV centers with limited spectral diffusion and high-quality factor cavity modes.

Two-dimensional Photonic Crystal Cavities in Bulk Single-crystal Diamond

Color centers in diamond are leading candidates for quantum information processing. Recent demonstra-tions of entanglement between separated spins of the nitrogen-vacancy (NV) color center constitute a major milestone in generating and distributing quantum in-formation with solid-state quantum bits. However, the generation of entanglement in local quantum nodes containing NV centers is an inefficient process due to the largely incoherent NV optical transitions, as the zero-phonon-line (ZPL) constitutes only 4% of the NV’s spontaneous emission. This fraction can be modified if the NV center is placed in a photonic cavity, which modifies the electromagnetic environment, and thus, the NV’s emission properties via the Purcell effect. Pho-tonic crystal (PhC) slab nanocavities offer high-quality factors (Q) and small mode volumes (V), which consid-erably increase the fraction of emission into the ZPL. Figure 1(A) shows the electric field profile in such a nanocavity, where the lattice constant is a = 214 nm and the thickness of the slab is H = a. The fabrication of such structures, however, typically requires laborious reactive-ion etching (RIE) thinning of a bulk diamond down to a thickness of H. This need arises because high-quality single-crystal diamond thin films are not available and the chemically inert nature of diamond precludes wet undercutting techniques. In this work, we fabricate PhC nanocavities in diamond directly from bulk diamond. Electron beam lithography and reactive ion etching (RIE) first defines the PhC structures, after which alumina deposited using atomic layer deposition conformally coats and protects the diamond sidewalls. Then, anisotropic oxygen plasma undercuts the diamond slabs and, finally, hydrofluoric acid removes the hard mask and alumina to reveal suspended diamond structures (Figure 1(B)). We find high Q resonances near the NV ZPL wavelength of 637 nm, as shown in the photoluminescence spectra in Figure 1(C). The fabrication details and cavity measurements are in the last reference.In conclusion, we report the first fabrication of photonic crystal slab nanocavities in bulk diamond. Immediate steps include the coherent coupling of a single NV center to the nanocavity, which will serve as a node in a quantum repeater and for solid-state cavity quantum electrodynamics investigations. This 2-D platform considerably expands the toolkit for classical and quantum nanophotonics in diamond.

Quasi-Bessel-Beam Generation using Integrated Optical Phased Arrays

Due to their unique diffractive properties, Bessel beams have contributed to a variety of important ad-vances and applications, including multiplane optical trapping, reduced scattering and increased depth of field microscopy, improved laser corneal surgery, and adaptive free-space communications. Recent work has turned toward generation of Bessel beams using com-pact form factors, including spatial light modulators, Dammann gratings, and metasurfaces. However, these demonstrations do not provide full on-chip integration, and most are fundamentally limited to static beam for-mation.In this work, integrated optical phased arrays, which manipulate and dynamically steer light, are proposed and demonstrated for the first time as a method for generating quasi-Bessel beams in a fully integrated, compact-form-factor system (Figure 1). First, the phase and amplitude distributions necessary for generating phased-array-based Bessel-Gauss beams are derived analogously to bulk-optics Bessel implementations. Next, a splitter-tree-based CMOS-compatible phased array architecture (Figure 2) is developed to passively encode arbitrary phase and amplitude feeding of the array – necessary for Bessel-Gauss-beam generation. Finally, the developed theory and system architecture are utilized to demonstrate a 0.64 mm × 0.65 mm aperture integrated phased array that generates a quasi-one-dimensional Bessel-Gauss beam with a ~14 mm Bessel length and ~30 μm power FWHM (Figure 3).

See-through Light Modulators for Holographic Video Displays

In this research (a collaboration with Dr. Daniel Smalley of Brigham Young University), we design and fabricate acousto-optic, guided-wave modulators in lithium nio-bate for use in holographic and other high-bandwidth displays. Guided-wave techniques make possible the fabrication of modulators that are higher in bandwidth and lower in cost than analogous bulk-wave acous-to-optic devices or other spatial light modulators used for diffractive displays; these techniques enable simul-taneous modulation of red, green, and blue light. In particular, we are investigating multichannel variants of these devices with an emphasis on maximizing the number of modulating channels to achieve large total bandwidths. To date, we have demonstrated multi-channel full-color modulators capable of displaying ho-lographic light fields at standard-definition television resolution and at video frame rates. Our current work explores a device architecture suitable for wearable augmented reality displays and other see-through applications, in which the light outcouples toward the viewer (Figure 1), fabricated using femtosecond laser micromachining (Figure 2).

A Scalable Single-photon Detector Array Based on Superconducting Nanowires

Detecting single photons over large numbers of spa-tial modes is crucial for photonic quantum informa-tion processing. This measurement usually requires an array of time-resolved single-photon detectors. The superconducting nanowire single-photon detec-tors (SNSPDs) are currently the leading single-photon counting technology in the infrared wavelength and have the highest performance in timing jitter, detection efficiency, and counting rate. In a conventional readout scheme, each SNSPD requires one coaxial cable in the cryostat, a low-noise RF amplifier, and a high-resolu-tion time-to-digital converter. Implementing a system of a few SNSPD channels with the conventional read-out is possible, but scaling them to tens or hundreds of channels requires formidable resources and remains an outstanding challenge.Here, we report a scalable two-terminal SNSPD array that only requires one pair of RF cables for the readout. Figure 1 shows the architecture of the array, where a chain of detectors was connected using superconducting nanowire delay lines. The nanowire delay lines were designed to be slow-wave transmission lines with a phase velocity of only 0.016c, where c is the speed of light in vacuum. When a detector absorbs a photon and fires, it generates a pair of counter-propagating pulses towards the two terminals. By registering the pulses on the two terminals, and performing simple timing logic, one can resolve the arrival locations of up to two incident photons (see Figure 2). By analyzing the electrical pulse shapes, we also showed photon-number-resolving capability in a 4-element device. This device architecture will be useful for multi-photon coincidence detection in photonic integrated circuits.

Utilization of BaSnO3 and Related Materials Systems for Transparent Conducting Electrodes

Efficient, transparent electrode materials are vital for applications in smart window, LED display, and solar cell technologies. These materials must possess a wide band gap for minimal optical absorption in the visible spectrum while maintaining high electrical conductivi-ty. Tin-doped indium oxide (ITO) has been the industry standard for transparent electrodes, but the use of the rare element indium has led to a search for better mate-rial alternatives. BaSnO3 represents a promising alter-native due to its high electron mobility and resistance to property degradation under oxidizing conditions, but the mechanisms by which processing conditions and de-fect chemistry affect the final material properties are not well understood.This work seeks to better understand the relationships between processing, defect chemistry, and material properties of BaSnO3, to better establish the consistent and controllable use of BaSnO3 as a transparent electrode. To accomplish these goals, methods such as in situ resistance and impedance monitoring during annealing will be applied. In addition, a variety of novel methods such as the in situ monitoring of optical transmission (shown in Figure 1) during annealing and the in situ monitoring of resistance during physical vapor deposition will be utilized to investigate BaSnO3. Direct measurements of the key constants for the thermodynamics and kinetics of oxidation in donor-doped BaSnO3 will be experimentally determined for the first time. This increase in understanding will provide a predictive model for determining optical properties, carrier concentrations, and electron mobilities in BaSnO3, which may be become increasingly important due to its high electron mobility, high-temperature stability, and favorable crystal structure.

A Sampling Jitter-tolerant Pipelined ADC

In a conventional pipelined ADC, the input signal is sampled upfront as shown in Figure 1. Any jitter in the sampling clock directly affects the sampled input and degrades the signal-to-noise ratio (SNR). Therefore, for fast varying input signals, the sampling jitter severe-ly limits the SNR. The error in sampled voltage due to clock jitter isΔv = (dv/dt) · Δtwhere dv/dt is the time-derivative of the input signal at the sampling instant and ∆t is the jitter in the sampling clock. Since the sampling clock jitter is random, it introduces a random noise in the sampled input signal. Also, the error voltage is proportional to dv/dt and hence to the amplitude and frequency of the input signal. Thus, as the frequency of the input signal increases, the effect of sampling clock jitter becomes more pronounced. In fact, it can be shown that for a known rms sampling jitter st the maximum SNR is limited toSNRmax = 1/(2πfinst )where fin is the input signal frequency. Typically, it is difficult to reduce the rms jitter below 100 fs. This limits the maximum SNR to just 44 dB (which is equivalent to 7 bits) for a 10 GHz signal. Therefore, unless the effect of sampling jitter is reduced, the performance of an ADC would be greatly limited for high frequency input signals. It has been shown that continuous-time delta-sigma modulators (CTDSM) reduce the effect of sampling jitter. But since CTDSMs rely on oversampling, they are not suitable for high frequency signals. Therefore it is imperative to develop sampling jitter-tolerant architectures for Nyquist-rate data converters. In this project, we propose a new topology that provides increased tolerance to sampling jitter. At present, we are designing the pipelined ADC in 16-nm CMOS technology to give a proof-of-concept for tolerance to sampling jitter.

A Pipelined ADC with Relaxed Op-amp Performance Requirements

Among various analog to digital converter (ADC) ar-chitectures, pipelined ADCs are well suited for appli-cations that need medium to high resolution above hundreds-of-megahertz sampling rate. To obtain good linearity, conventional pipelined ADCs must mini-mize multiplying digital to analog converter (MDAC) charge-transfer error by employing high-gain, fast-set-tling op-amps. However, such an op-amp design has become increasingly difficult due to the reduced in-trinsic gain and voltage headroom in a fine-line CMOS technology. With low intrinsic gain devices, either a gain-boosting technique or a multi-stage topology is necessary to make the op-amp meet the gain require-ment. Decreased power supply demands a larger capac-itance to maintain the same level of SNR. As a result, the power consumption of these op-amps becomes prohibitively large. Op-amp non-idealities have been removed or relaxed in digital domain by taking advantage of digital computation to address this issue. In this project, we propose a digital calibration scheme for op-amp-based pipelined ADCs. The ADC relaxes first stage op-amp performance requirements by using a shadow ADC and a simple digital domain calibration algorithm. To validate the functionality of the proposed calibration technique, a proof-of-concept ADC has been designed in 28nm CMOS technology and is currently being tested.

Data-dependent Successive-Approximation-Register Analog-to-Digital Converter

This work on successive-approximation-register (SAR) analog-to-digital converters (ADCs) (Figure 1) aims at improving data-dependent savings in energy in key components of a SAR ADC by leveraging the informa-tion available from signal’s immediate past samples and the signal type. The dominant energy consuming components are the digital-to-analog converter (DAC) and the comparator.Energy expenditure in the DAC per sample conversion depends on the DAC topology and sequence of steps taken during successive approximation. Energy in the comparator is directly proportional to the number of comparisons done per sample conversion. A design with data-dependent savings takes advantage of the correlation between successive samples in completing the conversion in fewer bit-cycles and also operates the DAC more energy-efficiently.Previous work presented data-dependent savings by doing least-significant-bit (LSB)-first successive approximation to convert an input sample. By starting with a previous sample and using LSB-first, the algorithm converges in a fewer number of cycles than conventional most-significant-bit (MSB)-first SAR conversion when the present signal is close to the previous signal. Fewer cycles translate into energy savings in the comparator and the DAC. Another work developed successive approximation algorithms to find a sub-range from the full range in a few cycles before carrying on a binary search in this small range. In this work, we investigate a SAR ADC with a search algorithm based on the statistical characteristics of the signal for optimum energy expenditure.

GaN HEMT Track-and-Hold Sampling Circuits with Digital Post-correction on Dynamic Nonlinearity for High-Performance ADCs

Analog-to-digital converters (ADCs) often limit the performance of integrated systems for emerging ap-plications such as next-generation communication systems, data centers, and quantum computing. The ADC performance is, in turn, limited at least partly by a track-and-hold sampling circuit (THSC). The low sup-ply voltage of deeply scaled complementary metal-ox-ide-semiconductor (CMOS) transistors determines the THSC input signal range, therefore becoming a fun-damental upper bound to the effective number of bits (ENOBs) of CMOS ADCs. This research work envisions to realize THSCs in GaN-on-Si technology, which monolithically integrates GaN high-electron-mobility transistors (HEMTs) with Si-CMOS transistors, for future ultrahigh-performance ADCs. Operating GaN HEMTs at a high voltage (>30 V) allows a very large input swing (>16 V), providing signal-to-noise ratio (SNR) performance orders of magnitudes beyond the limit of CMOS THSCs. We designed and implemented two GaN HEMT THSCs. The first THSC was fabricated in a commercial GaN foundry technology on SiC substrate, providing 98-dB SNR at 200 MS/s. The second THSC design was fabricated in a GaN technology that was developed at MTL on Si substrate, which operates at 1 GS/s thanks to a higher current-gain cutoff frequency fT and external gate-bootstrapping clock (Figure 1). While these GaN HEMT THSCs achieved an unprecedentedly high SNR at a given input frequency, they suffer from dynamic nonlinearity from the GaN HEMT source-follower buffers for gate-bootstrapping sampling clock generation. Although dynamic nonlinearity correction techniques are mature with RF power amplifiers (PAs), these conventional pre-distortion techniques have high sensitivity to DC offsets, and thus, cannot be directly applied to GaN HEMT THSCs.To overcome this challenge, we are developing a digital post-correction (DPC) technique, which will demonstrate improved linearity of GaN HEMT THSCs without using a dedicated reference ADC. By applying a DPC technique based on modified Volterra series (Figure 2), we have recently demonstrated that THSC linearity can be improved by more than 20 dB. We are presently working to enhance the linearization performance by applying advanced DPC techniques.

GaN Circuit-device Interaction in Fully Integrated RF Power Amplifiers

Highly integrated GaN RF power amplifiers (PAs) have been developed for mobile devices and connected cars ap-plications using the physics-based RF transistor compact model, MIT Virtual Source GANFET (MVSG). RF power amplifiers are required to operate in a linear region to prevent signal distortion and resultant data loss, which is mainly affected by inherent device-level nonlinear be-havior. Since the second derivative of transconductance, g3, is an intrinsic source of intermodulation distortion, many studies aimed to cancel it, especially in CMOS tech-nology. However, the high mobility and thermal effect of GaN devices make the device nonlinearity compensation harder than in CMOS devices. Thus, we have looked into the large signal linearization considering both power gain and third-order harmonics rather than g3 alter-ation techniques that cannot be properly functional in a high-power amplifier with large signal input.In our previous design, the Class-AB + Class-C configuration was proposed for a fully integrated GaN RF amplifier, demonstrating improved linearity and efficiency. Recently, we designed another GaN RF power amplifier with the Common-Source & Common Gate (CS-CG) configuration to further improve the intermodulation distortion by optimizing the third order harmonics performance from the viewpoint of compensating for the large signal distortion. The CS-CG outperforms the Class-AB + Class-C in terms of the third order harmonics and intermodulation distortion, which means that the average time-varying composite g3 of the CS–CG is lower than that of the Class-AB + Class-C.To study the impact of the device and technology parameters on the circuit performance, we used both the MVSG model and the CS-CG amplifier and isolated some device parameters which affect the DC and RF performance at both device and circuit levels. Figure 1 shows the circuit implementation using 0.25μm GaN technology and its gain and third- order harmonics with varying DIBL, δ. Intermodulation distortion is further investigated with varying δ, short channel effects such as moderate punch-through, nd, and parasitics, i.e., Cds, and Cdg, as depicted in Figure 2.

Cryptographically Secure Ultra-fast Bit-level Frequency Hopping for Next-generation Wireless Communications

Current Internet-of-Things devices communicate via Bluetooth Low Energy (BLE). Unfortunately, BLE-con-nected devices are vulnerable to a wide range of attacks; this work specifically addresses selective jamming denial of service where the adversary corrupts transmitted mes-sages targeting a single victim. Selective jamming is par-ticularly challenging as it conceals the attacker’s identity contrary to broadband-wireless jamming. To illustrate this type of attack, we demonstrate selective jamming against a commercial fitness BLE-device as shown in Figure 1. This form of attack can cause serious harm such as in the case of insulin pump medical devices.The primary vulnerability of BLE is founded in the communication protocol which uses frequency hopping to send a message, which is decomposed into data packets, over rapidly changing sub-frequencies. The carrier frequency hops among these sub-frequencies at a relatively slow rate of 612µs per data packet (Figure 2). Conversely, an attacker needs only 1µs to identify the carrier frequency, then block the remainder of the data packet sent on that sub-frequency. To counter this attack, we developed physical-layer security through an ultra-fast bit-level frequency hopping scheme which sends every data bit on a unique carrier frequency while achieving a 1µs hop period (Figure 2). In addition, a challenging issue is that traditional modulation schemes, such as the BLE Gaussian frequency shift keying (GFSK) modulation with fixed carrier offset of ± 250kHz for Bit 1 and Bit 0, permit the attacker to selectively overwrite individual bits in a packet once the carrier frequency is localized. The attacker gains control over the packet that will be received by the victim. We protect against this attack by implementing a cryptographically secure data-driven dynamic channel selection scheme that enables 80-way pseudorandom FSK modulation and provides data encryption in the physical layer.In this work, we demonstrated the first integrated bit-level frequency-hopping transmitter that hops at 1μs period and uses data-driven random dynamic channel selection to enable secure wireless communications with data encryption in the physical layer.

A Dense 240-GHz 4×8 Heterodyne Receiving Array on 65-nm CMOS Featuring Decentralized Generation of Coherent Local Oscillation Signal

There is a growing interest in pushing the frequency of beam-steering systems towards terahertz range, in which case narrow-beam response can be realized at chip scale. However, this calls for disruptive chang-es to traditional terahertz receiver architectures, e.g., square-law direct detector arrays (low sensitivity and no phase information preserved) and small heterodyne mixer arrays (bulky and not scalable). In the latter case, corporate feed for generating and distributing the local oscillation signals (LO)— typically a necessary component—can be very lossy at large scale. Here, we report a highly scalable 240-GHz 4×8 heterodyne array achieved by replacing the LO corporate feed with a net-work that couples LOs generated locally at each unit. A major challenge for this architecture is that each unit should fit into a tight λ/2×λ/2 area to suppress side lobes in beamforming, making the integration of the mixer, local oscillator, and antenna into a unit ex-tremely difficult. This challenge is well-addressed in our design. We have built highly-compact units, which ultimately enables the integration of two interleaved 4×4 phase-locked sub-arrays in 1.2-mm2.The schematic of the circuit of one unit is shown in Figure 1(a). Its core component is a self-oscillating harmonic mixer (SOHM), which can simultaneously (1) generate high-power LO signal and (2) down-mix the radio frequency (RF) signal. The SOHM is connected to both an intra-unit slot antenna (TL4 and TL4’) for RF receiving and a co-planar waveguide (CPW)/slotline mesh (TL3) for strong LO coupling with neighboring SOHMs. Owing to the coupling, LOs generated in each unit can be all locked to an external reference signal so that the array is coherent. Die photo showing the placement of the array and the PLL is given in Figure 1(b). Measured spectrum of 4.6-MHz (below the noise corner frequency) baseband signal is shown in Figure 2, from which we obtain a sensitivity (required incident RF power to achieve SNR=1 at baseband) over 1-kHz detection bandwidth of 38.8pW – more than 6× improvement over state-of-the-art large-scale homodyne arrays.

THz-Comb-Based Radar for Ultra-Broadband 3-D Imaging

Low-cost 3-D imaging recently becomes increasingly attractive because of its enormous potential in security applications. In particular, waves in the low terahertz (THz) range provide powerful capabilities for 3-D imag-ing due to the large available bandwidth and improved angular resolution (compared with radio frequency and mm-wave signals), and good transmission (<0.01 dB/m) through extreme weather conditions (compared with infrared and visible light).We propose a comb radar architecture to increase the bandwidth to more than 0.1 THz without using ultra-wideband components. Shown in Figure 1, it utilizes equally-spaced signal tones with frequency modulation; the generated IF signals are then combined in the digital domain. The proposed comb radar architecture has many advantages compared with conventional Frequency-Modulated Continuous-Wave (FMCW) radar in silicon: peak performance is maintained across a large bandwidth, finer Doppler frequency resolution, larger intermediate frequency (thus smaller flicker noise) and higher linearity. Similar to our previous frequency-comb-based THz spectrometer, in this radar, all components including antennas can be integrated on a single chip, our solution has merits of low cost, small volume, and lightweight.Figure 2 shows the architecture of the proposed comb radar. It consists of multiple channels with a suitable bandwidth in each channel, leading to an aggregated bandwidth that is larger than 0.1 THz. Note that the number of channels is not limited by the architecture, so the aggregated bandwidth is only limited by the bandwidth of a single channel. The FMCW signal is fed into the first channel directly and up-converted through single sideband mixers to the subsequence channels step by step. The transmitter and the receiver share one on-chip antenna to save the area and power. The mixer first receiver utilizes the transmit power as local oscillator signal and down-converts the received echo signal to IF for further image processing. In addition, since backside radiation has asymmetric radiation pattern and multiple reflections in the attached silicon lens, front-side radiation is desired. To this end, we adopt a substrate-integrated-waveguide antenna utilizing its multiple high-order resonance modes in orthogonal directions. Compared with patch antenna, the new on-chip antenna design has much wider bandwidth (>10% fractional bandwidth).

CMOS Chip-scale Vector Ambient Magnetic Field Sensing Based on Nitrogen-vacancy (NV) Centers in Diamond

Nitrogen-vacancy (NV) centers in diamond have attract-ed attention for spin-based quantum sensing in ambi-ent conditions. They have demonstrated outstanding nanoscale sensing and imaging capabilities for magnet-ic-fields. However, these sensing systems require many discrete devices to operate. This limits their scalability. In this work, we demonstrate a chip-scale CMOS and NV in-tegrated platform for magnetic field sensing. The CMOS chip performs the required spin manipulation and read-out functions for NV sensing protocols.Magnetic field sensing is accomplished by determining the spin states of the NV. The frequency of the spin states is determined by through optically detected magnetic resonance (ODMR). The magnetic field is proportional to the frequency splitting of the spin states (2.8 MHz/Gauss). Our system has an on-chip microwave (MW) signal generator, operating from 2.6 GHz to 3 GHz. In addition, an on-chip coil with parasitic loops radiates the AC magnetic field with an amplitude up to 10 Gauss with 95% uniformity over 50 µm x 50 µm. This MW radiation efficiently manipulates the NV spin ensembles. This is followed by on-chip optical readout of the spin state. A CMOS-compatible metal-dielectric structure filters out the optical pump (532 nm) with an isolation of 10 dB. An on-chip patterned P+/N-Well photodiode, beneath the MW coil and the filter, detects the NV red fluorescence. This photodiode is patterned to reduce the unwanted coupling to the MW coil. The measured photodiode responsivity is 230mA/W. The proposed system opens the door for a highly integrated quantum system with applications in the life sciences, tracking, and advanced metrology.

An Energy-efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications

End-to-end security protocols, like Datagram Trans-port Layer Security (DTLS), enable the establishment of mutually authenticated confidential channels be-tween edge nodes and the cloud, even in the presence of untrusted and potentially malicious network infra-structure. While this makes DTLS an ideal solution for IoT, the associated computational cost makes soft-ware-only implementations prohibitively expensive for resource-constrained embedded devices. We ad-dress this challenge through the design of energy-effi-cient hardware to accelerate the DTLS protocol along with associated cryptographic computations.Figure 1 shows a block diagram of our system, which consists of a 3-stage RISC-V processor, and a memory-mapped DTLS engine supporting the AES-128 GCM, SHA-256, and prime curve elliptic curve cryptography (ECC) primitives. We demonstrate hardware-accelerated DTLS which is 438x more energy-efficient and 518x faster than software implementations. The use of dedicated hardware for DTLS also reduces code size by 78KB and data memory usage by 20KB, thus increasing processor resources available to the application stack.The test chip, shown in Figure 2, was fabricated in a 65nm LP CMOS process, and it supports voltage scaling from 1.2V down to 0.8V. The RISC-V processor achieves 0.96DMIPS/MHz, consuming 40.36μW/MHz at 0.8V. The DTLS engine consumes 44.08μJ per DTLS handshake, and 0.89nJ per byte of application data, both at 0.8V. Therefore, through the design of reconfigurable energy-efficient cryptographic accelerators and a dedicated protocol controller, this work makes DTLS a practical solution for implementing end-to-end security on resource-constrained IoT devices.

Ultra-Low-Power, High-sensitivity Secure Wake-up Transceiver for the Internet of Things

The Internet of Things (IoT) connects together an ex-ponentially growing number of devices with an esti-mate of more than 70 billion devices in less than ten years from now. Such devices revolutionize the per-sonal heart monitoring, home automation, as well as the industrial monitoring systems. Unfortunately, the wireless IoT nodes consume a huge portion of their en-ergy on communicating with other devices. On the oth-er hand, a longer battery lifetime or even a batteryless energy-harvesting operation requires a sub-microwatt consumption without significant performance deg-radation. In this work, we propose protocol optimiza-tions as well as circuit-level techniques in the design of a -80dBm sensitivity ultra-low power wake-up receiver for on-demand communication with IoT nodes.Wireless protocols such as Bluetooth low-energy (BLE) are optimized for short-length packets with small preambles and reduced header sizes. However, the power consumption of a low duty-cycled node in the default connected-mode is limited by the periodic beacons dictated by the protocol. Commercial BLE chips are then limited to tens of microwatts even though their standby power is in the nanowatt range. This wake-up receiver exploits the lower limit of the standby power to achieve significant power reduction through a wake-up scheme wrapped around the BLE advertising protocol. The receiver, shown in Figure 1, employs such duty-cycled wake-up scheme to mitigate the power/sensitivity trade-off achieving sub-microwatt average power at the required BLE sensitivity. When the receiver decodes its wake-up pattern inside the BLE advertising packet, depicted in Figure 2, it generates a wake-up signal then reconfigures its correlator with a new pattern. Figure 3 illustrates the power/latency trade-off where a user with a commercial app can use a cellphone to wake any sleeping IoT node up using the BLE standard according to the application at hand.

Contactless Current Sensing for Industrial IoT

The ability to sense current is crucial to many industri-al applications including power line monitoring, motor controllers, battery fuel gauges, etc. We are developing smart connectors with current sensing abilities for use in the industrial internet of things (IoT). These connec-tors can be used for 1) power quality management: to measure real power, reactive power, and distortion, and 2) machine health monitoring applications for continu-ous monitoring, control, prevention, and diagnosis. At the system level, the smart connectors need to 1) mea-sure AC, DC, and multiphase currents, 2) reject stray magnetic fields, and 3) detect impending connector fail-ure. On the sensor level, they need to provide high mea-surement bandwidth (BW) and low power operation. Current can be sensed directly by using a shunt resistor, but it leads to large power dissipation for measuring high current levels (10-100 A). Indirect/contactless sensing, which senses the magnetic field strength, is a better option as it offers galvanic isolation and the ability to operate safely in high voltage applications. Examples of contactless current sensors include Hall, magneto-resistive (MR), and fluxgate (FG) sensors. FG sensors with integrated magnetics offer higher sensitivity than Hall sensors (nT vs. µT) and higher linearity and lower offset hysteresis than MR sensors, making them a good choice for industrial current sensing. The proposed system consists of a central processor and multiple low-power, high-BW FG sensors to make synchronous measurements (Figure 1). The measured data from all sensors is stored on the central processor, which runs preliminary analytics on the data before sending it to the cloud. Figure 2 shows the workings of a basic fluxgate sensor design. The proposed sensor makes use of various power saving techniques to reduce the energy per measurement, as well as digitally assisted analog circuits to push for high BW and BW scalability with duty cycling, from >100 kHz BW for machine health monitoring to <1 kHz for power quality management.

Navion: An Energy-efficient Accelerator for NanoDrones Autonomous Navigation in GPS-denied Environments

Drones are getting increasingly popular nowadays. Nanodrones specifically are easily portable and can fit in your pocket. Equipped with multiple sensors; the drone functionality is getting more powerful and smart (e.g., track objects, build 3-D maps, etc.). These ca-pabilities can be enabled by powerful computing plat-forms (CPUs and GPUs), which consume a lot of energy. The size and battery limitations of Nanodrones make it prohibitive to deploy. This work presents Navion, an energy-efficient accelerator for visual-inertial odometry (VIO) that enables autonomous navigation of miniaturized robots, and augmented reality on portable devices. The chip fuses inertial measurements and mono/stereo images to estimate the camera’s trajectory and a sparse 3-D map. VIO implementation requires large irregularly structured memories and heterogeneous computation flow. The entire VIO system is fully integrated on-chip to eliminate costly off-chip processing and storage. This work uses compression and exploits structured and unstructured sparsity to reduce on-chip memory size by 4.1x. Navion is fabricated in 65nm CMOS. It can process 752x480 stereo images at 171 fps and inertial measurements at 52 kHz, consuming an average 24mW. It is configurable for maximizing accuracy, throughput, and energy-efficiency across different environments. This is the first fully integrated VIO in an ASIC.

Fast Frontier-exploration for Unmanned Autonomous Vehicles with Resource Constraints

Unmanned Autonomous Vehicles (UAV) have received wide attention. Their capability to autonomously navigate around the environment enables many ap-plications including search-and-rescue, surveillance, wildlife protection and environment mapping. The key technique to empower such capabilities is the frontier-exploration algorithm, which periodically makes decisions on where the vehicle should explore next in an unknown environment based on previous-ly acquired knowledge. However, such algorithms are computationally expensive. In a practical system, the computation is usually offloaded to a powerful com-puter, causing a significant delay in the response time. This also makes the system strongly dependent on the presence of a stable wireless connection. These factors prohibit the application of the frontier-exploration al-gorithm to resource-constrained miniature UAVs with limited battery and computation power.In this work, we present an algorithm to reduce the computation cost of the state-of-the-art mutual information based frontier-exploration algorithm. The key idea behind the algorithm is to use the same computations between different parts of the mutual information computation and reduce redundant computations. Additionally, our approach seeks a more compact representation of the environment, which minimizes the number of operations required to run the algorithm.In practice, our algorithm enables the complicated frontier-exploration algorithm to be deployed to a battery-powered miniature UAVs with limited computation power. The algorithm makes it possible for the UAV to explore a closed unknown environment with no stable wireless connections. Thanks to the capability of local computation, the latency of running the algorithm is reduced, enabling the UAVs to explore faster and quickly react to the changes in the environment. The saved computation power can be allocated to the actuators of the UAV, enabling the UAVs to stay in the air longer and therefore explore a larger area given fixed power budget.

Efficient Processing for Deep Neural Networks

Artificial Intelligence powered by deep neural networks (DNNs) has shown great potential to be applied to a wide range of industry sectors. Due to DNNs’ high computa-tional complexity, energy efficiency has ever-increasing importance in the design of future DNN processing sys-tems. However, there is currently no standard to follow for DNN processing; the fast-moving pace in new DNN algorithm and application development also requires the hardware to stay highly flexible for different con-figurations. These factors open up a large design space of potential solutions with optimized efficiency, and a systematic approach becomes crucial.To solve this problem, we address the co-optimization among the three most important pillars in the design of DNN processing systems: architecture, algorithm, and implementation. First, we present Eyeriss, a fabricated chip that implements a novel data flow architecture targeting energy-efficient data movement in the processing of DNNs (Figure 1). Second, we develop Energy-Aware Pruning (EAP), a new strategy of removing weights in the network to reduce computation so that it becomes more hardware-friendly and yields higher energy efficiency (Figure 2). Finally, we present a tool to realize fast exploration of the architecture design space under different implementation and algorithmic constraints.

Energy-efficient Deep Neural Network for Depth Prediction

Depth sensing and estimation is a key aspect of posi-tional and navigational systems in autonomous vehi-cles and robots. The ability to accurately reconstruct a dense depth map of a surrounding environment from RGB imagery is necessary for successful obstacle de-tection and motion planning. Since deep convolutional neural networks (DNNs) have proven to be successful at achieving high accuracy rates in image classification and regression, recent work in the deep learning space has focused on designing neural networks for depth prediction applications. However, the high accuracy of DNN processing comes at the cost of high computa-tional complexity and energy consumption, and most current DNN designs are unsuitable for low-power applications in miniaturized robots. In this project, we aim to address this gap by applying recently developed methodologies for estimating and improving the ener-gy-efficiency of DNNs to an existing depth-prediction DNN. We envision an outcome in which the depth-pre-diction DNN is modified to be better suited for a spe-cialized hardware implementation that could be in-tegrated with a low-power visual-inertial odometry system to result in a combined navigational system for miniaturized robots.

Depth Estimation of Non-Rigid Objects for Time-of-Flight Imaging

Depth sensing is used in a variety of applications that range from augmented reality to robotics. Time-of-flight (TOF) cameras, which measure depth by emitting and measuring the roundtrip time of light, are appeal-ing because they obtain dense depth measurements with minimal latency. However, as these sensors be-come prevalent, one disadvantage is that many TOF cameras in close proximity will interfere with one an-other, and techniques to mitigate this can lower the frame rate at which depth can be acquired. Previously, we proposed an algorithm that uses concurrently col-lected optical images to estimate the depth of rigid ob-jects. Here, we consider the case of objects undergoing non-rigid deformations. We model these objects as lo-cally rigid and use previous depth measurements along with the pixel-wise motion across the collected optical images to estimate the underlying 3-D scene motion, from which depth can then be obtained. In contrast to conventional techniques, our approach exploits previ-ous depth measurements directly to estimate the pose, or the rotation and translation, of each point by find-ing the solution to a sparse linear system. We evaluate our technique on a RGB-D dataset where we estimate depth with a mean relative error of 0.58%, which out-performs other adapted techniques.

Small-footprint Automatic Speech Recognition Circuit

With the advanced technology of speech and natural language processing, spoken language has become a feasible way for human-machine interaction. Due to the high complexity of articulated speech signal, au-tomatic speech recognition (ASR) generally requires intensive computation and memory size to achieve good performance. However, due to its widespread ap-plications on robots, wearables, and mobile devices, it’s desirable to design circuit to implement ASR locally in a resource-limited environment, particularly in which power consumption is a critical concern.In this work, we first scrutinize software speech recognition procedure; evaluate the memory and computational resource needed when transferring to hardware, and take advantage of circuit design to minimize size and power usage. We design small-footprint ASR system (Figure 1) with cutting-edge neural network that can best perform acoustic modeling with memory restrictions, along with weight truncation and quantization. Dedicated arithmetic unit design, parallelization, and resource dispatching further reduce latency. We implement weighted finite-state transducer (WFST) to incorporate the phonetic probability with language model to select the best word transcription. Model compression, caching, and lattice truncation are adopted to adapt the ASR to circuit and optimize the design. Our ASR design leveraging powerfulness and robustness of neural network in hybrid ASR model outperforms conventional model in recognition accuracy, whereas conducting ASR tasks on-chip sees great reduction in power compared to CPU. We show a 2.4X reduction in neural network weight size compared to previous hardware design. Our work demonstrates the feasibility to operate an ASR in a small-footprint environment in applications with small vocabulary size and optimized model.

In-Memory Computation for Low Power Machine Learning Applications

Convolutional Neural Networks (CNN) have emerged to provide the best results in a wide variety of ma-chine learning (ML) applications, ranging from image classification to speech recognition. However, they require huge amounts of computation and storage. When implemented in the conventional von-Neumann computing architecture, there is a lot of data move-ment per computation between the memory and the processing elements. This leads to a huge power con-sumption and long computation time, making CNNs unsuitable for many energy-constrained applications, e.g., smartphones, wearable devices, etc. To address these challenges, we propose embedding computation capability inside the memory (Figure 1). By doing that, we can significantly reduce data transfer to/from the memory and also access multiple memory addresses in parallel, to increase processing speed. The basic convo-lution operation in a CNN layer can be simplified to a dot-product between the layer inputs (X) and the filter weights (w), to generate the outputs (Y) for that layer. In this work, CNNs are trained to use binary filter weights (w = +/- 1), which are stored as a digital ‘0’ or ‘1’ in bit-cells of the memory array. The digital inputs (X) are converted to analog voltages and sent to the array, where the dot-products are performed in the analog domain. Finally, the analog dot-product voltages are converted back into the digital domain outputs (Y) for further processing.To demonstrate functionality for a real CNN architecture, the Modified National Institute of Standards and Technology (MNIST) handwritten digit recognition dataset is used with the LeNet-5 CNN (Figure 2). We demonstrated a classification accuracy of 98.35%, which is within 1% of what can be achieved with an ideal digital implementation. We achieved more than 16x improvement in the energy-efficiency in processing the dot-products vs. full-digital implementations. Thus our approach has the potential to enable low-power ubiquitous ML applications for smart devices in the Internet-of-Everything.

Reconfigurable Neural Network Accelerator using 3-D Stacked Memory Supporting Compressed Weights

The recent success of machine learning, with the help of emerging techniques, such as convolutional neural networks, have been rapidly changing the way many traditional signal processing problems are being solved, including vision processing, speech recognition, and other prediction and optimization problems. Howev-er, neural networks require a large number of weight parameters and processing power that are difficult to accommodate efficiently using a normal CPU architec-ture. This necessitates dedicated on-chip solutions. A major challenge in recent on-chip neural network processors is reducing the energy consumed by memory accesses, as the cost for data operations becomes relatively cheaper than the cost for data movement in recently advanced processes. One approach is to simply reduce the amount of data movement by using compression schemes (i.e., reducing the bit-width of weights and activations). Han, et al. develop a deep compression technique to non-uniformly quantize floating point weights to 4-bit values, without any loss of accuracy. This was further extended to quantizing to only 2-bit ternary weights. Another approach is to increase the memory capacity, for example with 3-D stacked memory, to reduce the required number of costly external DRAM accesses.Our proposed design takes full advantage of these compression schemes by directly integrating the decompression within the processing element. In addition, the design can be reconfigured to perform more general fixed-point computations with variable bit-widths. Combining this with a closely integrated memory chip through 3-D stacking makes it possible to run large networks with less data movement to and from the external DRAM, resulting in improved energy efficiency compared to other implementations.

Bandwidth-efficient Deep Learning: Algorithm and Hardware co-Design

In the post-ImageNet era, computer vision and ma-chine learning researchers are solving more complicat-ed Artificial Intelligence (AI) problems using larger data sets driving the demand for more computation. How-ever, we are in the post-Moore’s Law world where the amount of computation per unit cost and power is no longer increasing at its historic rate. This mismatch be-tween supply and demand for computation highlights the need for co-designing efficient machine learning al-gorithms and domain-specific hardware architectures. By performing optimizations across the full stack from application through hardware, we improved the efficiency of deep learning through smaller model size, higher prediction accuracy, faster prediction speed, and lower power consumption. Our approach starts by changing the algorithm, using “Deep Compression” that significantly reduces the number of parameters and computation requirements of deep learning models by pruning, trained quantization, and variable length coding. “Deep Compression” can reduce the model size by 18× to 49× without hurting the prediction accuracy. We also discovered that pruning and the sparsity constraint not only applies to model compression but also applies to regularization, and we proposed dense-sparse-dense training (DSD), which can improve the prediction accuracy for a wide range of machine learning tasks. To efficiently implement “Deep Compression” in hardware, we developed EIE, the “Efficient Inference Engine,” a domain-specific hardware accelerator that performs inference directly on the compressed model which significantly saves memory bandwidth. Taking advantage of the compressed model, and being able to deal with the irregular computation pattern efficiently, EIE improves the speed by 13× and energy efficiency by 3,400× over GPU.

Ultra-thin, Reconfigurable, High-efficiency Meta-optical Devices in Mid-infrared

The mid-infrared (MIR) is a frequency band strategi-cally important for numerous biomedical, military, and industrial applications. Further development of MIR devices is hindered by the lack of inexpensive and efficient basic optical elements such as lenses, wave plates, filters, etc. Furthermore, the available compo-nents are typically bulky and passive. Our research ad-dresses these challenges by leveraging novel low-loss optical phase-change materials (Ge-Sb-Se-Te) and their sub-wavelength patterning to achieve ultra-thin (thick-ness < 0/5), high-efficiency (>25%), and multi-function-al MIR components. As a proof-of-principle, we demonstrated a reconfigurable bifocal meta-lens with a switchable focus. Our metalens principle is based on collective Mie scattering of incident plane waves by subwavelength dielectric structures, which sustain both electric and magnetic dipolar resonances. Each of the scatterers, also known as Huygens’ meta-atoms, contributes to the phase and amplitude of the incident beam. The amount of phase shift was controlled by the meta-atom geometry and its refractive index. Proper spatial arrangement of meta-atoms can reconstruct a desired phase profile. For instance, lens functionality can be achieved by introducing a hyperboloid phase distribution. In amorphous state (A-state) the lens focuses the incident light at a focal length of 1 mm; after the heating-induced material state transition, the focal length changes to 1.5 mm (C-state). The switching of the focal length was attained by changing the hyperboloidal phase profiles. For simplicity, we performed binary discretization of original continuous phase distributions: 0° and 180° phase shifts. Then, we formed a library of four distinct meta-atoms that can realize the binary transitions. The metalens was fabricated by depositing a 1-m-thick Ge2Sb2Se4Te1 film onto CaF2 substrate followed by patterning processes involving electron-beam lithography patterning and reactive ion etching with a mixture of fluoromethane gases. We believe that our findings will enable a new range of compact, multi-functional spectroscopic, and thermal imaging devices.

Reprogrammable Electro-Chemo-Optical Devices

Photonic devices with programmable properties allow more flexibility in the manipulation of light. Recently, several examples of reconfigurable photonic devices were demonstrated by controlling the local/overall in-dex of refraction in thin films, either by a thermally induced phase change in chalcogenides or by interca-lation of lithium into oxides. We propose a novel ap-proach for design of reprogrammable photonic devices based on electrochemical modification of ceria-based electro-chemo-optical devices. Previously, it was shown that the refractive index of PrxCe1-xO2-δ (PCO) is a function of oxygen nonstoichiometry δ , that can be controlled electrochemically via closely spaced electrodes in a lateral device configuration. For transverse modified configurations, a PCO thin film on yttrium-stabilized zirconia (YSZ) substrate with transparent conducting oxide (TCO) top electrode allows for voltage-controlled oxygen exchange. Enhanced spatial resolution can be further achieved with the aid of lithographically patterned nano-dimensioned oxide layers.

Y-Branch Compact Model Including the Line Edge Roughness Effect

Silicon photonics is a booming design platform due to its ability to support high data rates and enable novel applications. Since the CMOS fabrication infrastruc-ture is leveraged in silicon photonics, it becomes crucial to provide process-variation-aware compact models as optical components inherit the process variations found in CMOS. These models would help designers, enhance yield, and serve as a building block in the sili-con photonics process design kit (PDK). We develop a compact model for a basic photonic component, a Y-branch, that specifies the variations in the transfer characteristics against line-edge roughness (LER). LER is a common statistical random process variation that causes imbalanced transmission between the two output ports of the Y-branch, which is supposed to be balanced. As a random process variation, LER affects the Y-branch transmission in a random behavior, so the transmission can be described by its mean (µ) and variance (σ2). This model provides the transmission mean and variance as a function of LER parameters, amplitude (A) and correlation length (LC), across the operating wavelength range of interest (λ). The flow of modeling, shown in Figure 1, starts by simulating different A and LC combinations with multiple instantiations for each to get a statistical sense of the variations. Afterward, the optical behavior of the Y-branch with the imposed LER is extracted and used to develop the compact model. The model is developed using the Gaussian process regression method where the R2 score for both mean and variance predictions is 0.99. Figure 2 shows the model’s performance on test data for predicting mean and variance. This model can be used in photonic integrated circuit simulators to predict the performance across process variations and worst corner cases as the models we rely upon in CMOS design.

Particle Defect Yield Modeling for Silicon Photonics

Silicon photonics, where photons instead of electrons are manipulated, shows promise for higher data rates, lower energy communication and information process-ing, biomedical sensing, and novel optically based func-tionality applications such as wavefront engineering and beam-steering of light. In silicon photonics, both electrical and optical components can be integrated on the same chip, using a shared silicon integrated circuit (IC) technology base. However, silicon photonics does not yet have a mature process, device, and circuit vari-ation models for the existing IC and photonic process steps; this lack presents a key challenge for design in this emerging industry.Our goal is to develop key elements of a robust design for manufacturability methodology for silicon photonics. As one part of the goal, here we focus on the impact of particle defects in silicon photonics, which can arise in photolithography, deposition, etching, and other processes. The model and result will be used to help generate layout design rules and critical area extraction methods, predicting and optimizing the yield of complex silicon photonic devices and circuits for tomorrow’s silicon photonics designers, just as IC designers do today.We model the impact of different types of particle defects (Figure 1) on different device components, e.g., straight waveguides (Figure 2) and y-splitters (Figure 3). We modify and apply the adjoint method, which is widely used in optimization, to accelerate the speed of simulation and reduce numerical error. The result from the adjoint method shows good consistency with direct simulation over different types of particles, different device components, and wavelengths ranging from 1500 to 1600 nm. The same methodology can be used on the circuit level and thus predict the yield of the chip. Present research also focuses on generating layout design rules and critical area extraction based on results from the adjoint method.

See-through Light Modulators for Holographic Video Displays

In this research, we design and fabricate acousto-optic, guided-wave modulators in lithium niobate for use in holographic and other high-bandwidth displays. Guid-ed-wave techniques make possible the fabrication of modulators that are higher in bandwidth and lower in cost than analogous bulk-wave acousto-optic devices or other spatial light modulators used for diffractive displays; these techniques enable simultaneous modu-lation of red, green, and blue light. We are investigating multichannel variants of these devices with an emphasis on maximizing the number of modulating channels to achieve large total bandwidths. To date, we have demonstrated multichannel full-color modulators capable of displaying holographic light fields at standard-definition television resolution and video frame rates. Our current work explores a device architecture suitable for wearable augmented reality displays and other see-through applications, in which the light outcouples toward the viewer (Figure 1), fabricated using femtosecond laser micromachining (Figure 2).

Bio-inspired Photonic Materials: Producing Structurally Colored Surfaces

Advances in science and engineering are bringing us closer and closer to systems that respond to human stimuli in real time. Scientists often look to biology for examples of efficient, spatially tailored multifunctional systems, drawing inspiration from photonic structures like multilayer stacks similar to those in the morpho butterfly. In this project, we develop an understand-ing of the landscape of responsive, bio-inspired, and active materials, drawing on principles of photonics and bio-inspired material systems. We are exploring material processing techniques (starting with electron beam lithography and moving to direct laser writing) to produce and replicate structurally colored surfaces while developing simulation and modeling tools (such as inverse design processes) to generate new structures and colors. Such complex biological systems require advanced fabrication techniques. Our designs are re-alizable through fabrication using direct laser writing techniques such as two-photon polymerization. We aim to compare our model system and simulations to fabricated structures using optical microscopy, scan-ning electron microscopy, and angular spectrometry. This process provides a toolkit with which to examine and build other bio-inspired, tunable, and responsive photonic systems and expand the range of achievable structural colors.Unlike with natural structures, producing biomimetic surfaces allows researchers to test beyond tunability that occurs naturally and explore new theory and models to design structures with optimized functions. The benefits of such biomimetic nanostructures are plentiful: they provide brilliant, iridescent color with mechanical stability and light-steering capabilities. By producing biomimetic nanostructures, designers and engineers can capitalize on unique properties of optical structural color and examine these structures based on human perception and response.

Reversible Electrothermal Switching of Nonvolatile Metasurfaces Based on Optical Phase Change Materials

Chalcogenide phase change materials (PCMs) are high-ly attractive for active metasurface applications due to their nonvolatile switching capability. So far, revers-ible switching of PCM-based metasurfaces is realized via either laser pulsing or electrical-current-induced phase transition. Both methods require raster-scanned writing and bulky off-chip instruments (lasers or AFM setups), making them incompatible with large-scale on-chip integration. A robust and scalable, on-chip, PCM-based metasurface switching method is therefore high-ly desired. Here we report an electrothermal switching method employing on-chip metal heaters, enabling large-area reversible switching for PCM-based meta-surfaces.Figure 1a shows the optical constants of the low-loss optical PCM (O-PCM) we choose for this application: Ge2Sb2Se4Te1 (GSST), which exhibits low-loss at both its amorphous and crystalline phases over a broad spectral range. Moreover, its improved amorphous phase stability gives rise to a larger critical switching thickness than that of traditional PCMs (e.g., GST-225). These two factors make GSST a preferred material for metasurface applications. Figure 1b illustrates the design of the switching platform. Ti/Pt are used as a metal heater for its excellent conductivity. After an atomic layer deposition of Al2O3, GSST is subsequently deposited and patterned via electron beam lithography. The thickness of the GSST meta-atoms is designed to be 220 nm. Finally, a SiO2 capping layer is deposited to prevent oxidation and evaporation of the PCM. The devices are wire-bonded onto a custom printed circuit board carrier to enable in-situ Raman and Fourier transform infrared (FTIR) characterizations. Figure 1c shows the SEM and optical microscope images of a fabricated device. The boundary of the heat is optimized for uniform heating in the PCM area. Figure 1d confirms the complete reversible switching of the PCM utilizing the distinct Raman peaks of amorphous and crystalline states. Figure 1e shows that more than 40% reflection contrast is achieved using this platform. Figure 1f, on the other hand, demonstrates that applying different voltages can achieve any arbitrary levels of crystallization, therefore providing possibilities for quasi-continuous tuning using this platform.

Graphene Microheaters for Controlled Switching of Optical Phase Change Materials

The integration of optical phase change materials (O-PCMs) into photonic devices enables a long-sought functionality: nonvolatile reconfiguration, the ability to switch between at least two distinct configurations with no power consumption to retain either one. Ener-gy-efficient, highly cyclable integrated optical devices such as switches, memories, metasurfaces, color pixels, and brain-inspired computing elements are success-ful examples of O-PCMs applications. However, these results use optical switching mechanisms that are challenging to scale up for architectures comprising hundreds of large-area active cells. To tackle this chal-lenge, we present a hybrid electro-optical framework in which we use graphene microheaters for thermal switching of Ge2Sb2Se4Te1 (GSST). We choose GSST be-cause of its broadband transparency in the infrared be-yond 18.5-µm wavelengths in both the amorphous and the crystalline states. Similarly, we choose graphene for our integrated approach because of its minimal optical loss (~ 0.1–1.2 dB/mm), high thermal conductivity, and stability. Such a device benefits from scalable electrical control, while having a reconfigurable optical response.We demonstrate large-area switching of 50-nm thick, 4×3-µm2 GSST using a 5×10-µm2 graphene heater (Figures 1A and 1B). The chip was wire-bonded onto a printed circuit board to enable in-situ Raman probing while electrically testing each integrated device (Figures 1C and D). To switch the as-deposited GSST to the crystalline state (heat up over ~280°C), we used 6V pulses with varying lengths between 10-20 ms. To reamorphize (melt over 650°C and quench), we triggered 13-µs electrical pulses with a peak voltage of 7.5V. We demonstrate repeatable electrical switching by in-situ Raman spectroscopy of GSST after each pulse excitation (Figure 1E), done by tracking the amorphous and crystalline signature peaks at 159 cm-1 and 120cm-1, respectively (Figure 1F). Furthermore, the change in color observed in the inset microscope images of Figure 1F demonstrates the nonvolatile modulation of the optical properties upon GSST switching.

Highly Sensitive Nanogap-based Mechanical Sensors for Infrared Detection

Many new physical phenomena show up only on na-noscale structures; with these phenomena, we can design novel devices with unprecedented functional-ity. Nanoengineering makes it possible to fabrication nanometer-sized quantum tunneling barriers that can be tuned mechanically. Such a tremendous mechanical tunability can be harnessed for mechanical sensors and many other types of sensors with extremely high sen-sitivity. Here we demonstrate two nanostructures that implement such a mechanically tunable tunneling barrier and use them for either a mechanical/strain sensor or a mid-infrared bolometric detector. The first nanostructure is the self-assembled graphene nanoflake network (Figure 1 (a)). It is composed of a resistance network of sub-micron graphene flakes that connect with <100 nm overlap. The second nanostructure is a metal nanogap with the gap defined by self-assembled monolayers (SAMs) (Figure 1 (b)). The proposed structures show high gauge factors and/or improved linear dynamic range as strain sensors (Figure 1 (c)). Such mechanical sensors can also be integrated with a thermal actuator to realize a highly sensitive, uncooled bolometer-type mid-infrared detector (Figure 2(a) and (b)). The measured temperature coefficient of resistance (TCR) can be as high as 5 K-1, which is more than one order of magnitude better than the state of the art (Figure 2(c)).

Oxide Passivation on MoS2-based Field-effect Transistors for Sensing Applications

Two-dimensional materials have attracted much at-tention as candidates for next-generation sensing platforms because of their unique electrical, optical, mechanical, and chemical properties. Due to its natural bandgap, MoS2 is one of the most popular two-dimen-sional materials for sensing. The sensing signal can be amplified as charges transfer onto the MoS2 channel and result in strong modulations in current with the present of the analyte. The large surface-to-volume ra-tio also contributes to the high sensitivity of a MoS2-based sensor. However, high sensitivity also results in much noise as vapor molecules and other interfering molecules absorb on the exposed MoS2 surface. Also, unprotected MoS2 can degrade in an ambient envi-ronment due to oxidation and surface contaminants. Therefore, a suitable passivation layer is needed to pro-tect the channel surface but still preserve the sensitiv-ity of MoS2.In this work, back-gated MoS2 field-effect transistors (FETs) were fabricated, and a thin layer of Al2O3 was deposited to passivate the channel surface. Prior to atomic layer deposition of Al2O3 as a seed layer, 2 nm of aluminum was deposited. Approximately 13 nm of Al2O3was added to the final device. With the oxide passivation, the hysteresis of both output and transfer characteristics was greatly reduced, indicating effective protection from fast absorbent-type trapping site. The sensing ability of oxide-passivated MoS2 FETs was also tested with a series of the electrolyte solution of pH ranging from 5 to 10. As shown in Figure 2, a near-linear relationship between relative change in resistance and change in pH was achieved. This work proves that Al2O3is a great passivation layer for MoS2-based sensor devices. With oxide being the outmost layer, other oxide-compatible surface functionalization can also be used to improve the selectivity of such sensors while still benefiting from MoS2’s natural sensitivity.